3.3.10. Target latency Register

The tgt_latency Register characteristics are:


Target latency, in cycles, for the regulation of reads and writes. A value of 0 corresponds to no regulation. See Latency regulation for more information.

Usage constraints

There are no usage constraints.


Only available when you select latency regulation in AMBA Designer.


Figure 3.10 shows the bit assignments.

Figure 3.10. tgt_latency Register bit assignments

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Table 3.11 shows the bit assignments.

Table 3.11. tgt_latency Register bit assignments

[31:28]-Reserved. Do not modify. Read as zero.
[27:16]ar_tgt_latencyAR channel target latency.
[15:12]-Reserved. Do not modify. Read as zero.
[11:0]aw_tgt_latencyAW channel target latency.

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