2.2.5. Latency regulation

The regulator achieves latency regulation by modifying the AxQOS value of each transaction request. This overrides any AxQOS value that the NIC-301 base product has specified, if any. If the interconnect and the addressed slave treat this as a priority value, then it has the required regulatory effect. For example, if a transaction is given an AxQOS value that gives it a higher priority, then this tends to reduce the latency of that transaction. In this way, a feedback loop is set up so that when the actual latency is higher than the target latency, the AxQOS value is proportionately raised, and the larger the latency discrepancy, the higher the priority.

Note

Where AxQOS is either ARQOS or AWQOS.

Latency regulation is useful for masters that have performance that is directly dependent on transaction latency. For example, a processor might be stalled while it waits for data after a cache miss.

You program the target latency separately for writes and reads. You enable latency regulation by setting the appropriate control bits in the control register. See Chapter 3 Programmers Model.

When you enable latency regulation for reads or writes, the base product AxQoS values are not used.

You set the range of AxQOS values used for latency regulation by programming the minimum and maximum values for writes and reads.

You program a scaling factor to give control over how quickly the AxQOS values change. The smaller the scaling factor, the more slowly the AxQOS values change in response to changes in latency. The scaling factor is specified as powers of two. See Chapter 3 Programmers Model.

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