3.3.1. QoS control Register

The qos_cntl Register characteristics are:

Purpose

The QoS control register contains the enable bits for all the regulators. By default, all of the bits are set to 0, and no regulation is enabled.

Usage constraints

Regulation only takes place when both the enable bit is set, and its corresponding regulation value is non-zero. This enables you to perform an integration test without activating the regulation. The QoS regulators are reset whenever they are re-enabled.

Configurations

Available in all QoS-301 configurations.

Attributes

Figure 3.1 shows the bit assignments.

Figure 3.1. qos_cntl Register bit assignments

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Table 3.2 shows the bit assignments.

Table 3.2. qos_cntl Register bit assignments

BitsNameFunction
[31:8]-Reserved. Do not modify. Read as zero.
[7]en_awar_ot[a]Enable combined regulation of outstanding transactions.
[6]en_ar_ot[a]Enable regulation of outstanding read transactions.
[5]en_aw_ot[a]Enable regulation of outstanding write transactions.
[4]en_ar_latency[b]Enable regulation of AR latency.
[3]en_aw_latency[b]Enable regulation of AW latency.
[2]en_awar_rate[c]Enable combined AW/AR rate regulation.
[1]en_ar_rate[c]Enable AR rate regulation.
[0]en_aw_rate[c]Enable AW rate regulation.

[a] If you include outstanding transaction regulation, you can configure en_awar_ot, en_ar_ot, and en_aw_ot. Otherwise, these bits, bits [7:5] are reserved, read as zero, and you cannot modify them.

[b] If you include latency regulation, you can configure en_ar_latency and en_aw_latency. Otherwise, these bits, bits [4:3] are reserved, read as zero, and you cannot modify them.

[c] If you include transaction rate regulation, you can configure en_awar_rate, en_ar_rate, and en_aw_rate. Otherwise, these bits, bits [2:0] are reserved, read as zero, and you cannot modify them.


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