3.2. Register summary

Table 3.1 shows the registers in offset order from the base memory address.

Table 3.1. Register summary

Offset

Name

Type

Reset

Width

Description

0x000-0x0FF----Reserved
0x100read_qosRW04CoreLink™ NIC-301 Network Interconnect read_qos register. See the CoreLink NIC-301 Network Interconnect Technical Reference Manual for information about this register.
0x104write_qosRW04CoreLink NIC-301 Network Interconnect write_qos register. See the CoreLink NIC-301 Network Interconnect Technical Reference Manual for information about this register.
0x108fn_modRW02CoreLink NIC-301 Network Interconnect fn_mod register. See the CoreLink NIC-301 Network Interconnect Technical Reference Manual for information about this register.
0x10Cqos_cntlRW08QoS control Register
0x110max_otRW06, 8, 6, 8Maximum number of outstanding transactions Register
0x114max_comb_otRW07, 8Maximum number of combined transactions Register
0x118aw_pRW08AW channel peak rate Register
0x11Caw_bRW016AW channel burstiness allowance Register
0x120aw_rRW012AW channel average rate Register
0x124ar_pRW08AR channel peak rate Register
0x128ar_bRW016AR channel burstiness allowance Register
0x12Car_rRW012AR channel average rate Register
0x130tgt_latencyRW012, 12Target latency Register
0x134kiRW03, 3Latency regulation Register
0x138qos_rangeRW04, 4, 4, 4QoS range Register
0x13C-0xFFF----Reserved

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