2.2.3. Transaction rate regulation

A variant of the standard internet Traffic SPECification (TSPEC) specifies the transaction rate regulation using the following parameters:

p

Peak rate.

b

Burstiness allowance.

r

Average rate.

You can independently program and enable the regulation of the read and write address channels with their own control bits. Alternatively, you can select combined regulation of the read and write address channels using another control bit. See Chapter 3 Programmers Model.

The request arrival curve, that A. TSPEC traffic upper bound, in Figure 2.3 shows, represents the characteristics imposed on the request flow, or flows.

Figure 2.3. TSPEC traffic specification

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The TSPEC parameters define an upper bound that applies over any time window.

B. Traffic bounded by TSPEC in Figure 2.3 illustrates this, with the accumulated data curve bounded by the TSPEC curve from any point in the data sequence. You program the TSPEC parameter values for AW and AR request rates in separate sets of registers. See Chapter 3 Programmers Model.

The regulators are disabled after reset.

If you program the regulators while they are enabled, the new values take effect immediately. Alternatively, you can disable the regulators, update the values, and then re-enable the regulators.

Binary fractions in transfers per cycle provide the values for peak and average rates.

So, for example, a value of 0x800, that is, 0.5 in decimal, sets a rate of one transfer every two cycles.

A value of 0x100, that is, 0.0625 in decimal, sets a rate of one transfer every 16 cycles.

A value of 0x000 sets a rate of one transfer per cycle, that is, no regulation. If you set either the burstiness to 0, or the average rate to 0, this disables the regulation of burstiness and average rate, (b,r).

In the same way, if you set the peak rate to 0, this disables the peak rate regulation. You can set:

Example 2.3. How to program the TSPEC regulator registers

If you require the transaction rate to be 1 transaction every 400 clock cycles, and each transaction is a 16-beat burst, program the peak rate, p, burstiness allowance, b, and average rate, r, registers as this example describes.

Transactions are only regulated on AW and AR transfers, so the burst length has no direct effect. A single transaction every 400 clock cycles is equivalent to a decimal fraction of 0.0025. This results in an infinite binary fraction, but an approximation to 12 bits is:

12'b000000001010

This value is approximated to 12 bits because the average rate register is 12 bits. See AW channel average rate Register and AR channel average rate Register.

When you convert this approximation back, it is equivalent to a decimal fraction of 0.00244140625, and this fraction is equivalent to 1 transaction every 409.6 clock cycles.

If you do not set all three TSPEC values, you can set either the peak rate only, or the burstiness and average rate, without the peak rate.

The peak rate register, p is only 8 bits, not 12 bits like the average rate register, r, so the previously calculated value does not fit. See AW channel peak rate Register and AR channel peak rate Register. Therefore, you can achieve hard regulation at 1 transaction in 409 clock cycles by setting the following:

The burstiness allowance, combined with the peak rate and average rate, enables variance in the issuing rate from that master during different system loadings. For example, set the values as follows:

This permits an issuing rate of 1 transaction every 200 clock cycles until the burstiness allowance, b, number of outstanding transactions is reached, and then, an average issuing rate, r, of 1 transaction every 409 clock cycles until the number of outstanding transactions drops below the burstiness allowance, b.


Combined AW and AR transaction rate regulation

You can regulate the combined transaction rate from the AW and AR channels. When you select this mode, QoS ignores the individual channel rates. QoS takes the TSPEC parameter values for the AW and AR channels combined from the AW values. See Chapter 3 Programmers Model.

Because two channels support twice the rate of a single channel, QoS scales the TSPEC parameters, for combined regulation, by a factor of two. For example, to specify a combined average rate of one transfer every eight cycles, set the value to 0x100. This is equal to two transfers every 16 cycles. This means that the rate you program is half the desired combined rate.

When the combined AW and AR channel traffic is so close to the TSPEC boundary that only one transfer is permitted, but both channels are requesting, then the regulator admits the AW channel and AR channel alternately.

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