A.13. MBIST interface

The width of the MBIST interface signals varies depending on whether ECC is implemented or not. In addition, DTCM can be run at speed and is accessed through the same port as L1 RAM. ITCM has its own dedicated interface.

Table A.41 shows the L1 and DTCM signals for designs without ECC.

Table A.41. L1 and DTCM Cortex-R7 MBIST interface width without ECC

NameTypeSource/destinationDescription
MBISTACK1[1:0]OutputMBIST controller

BIST mode acknowledge signal:

0

Enabled.

1

Not enabled.

MBISTREQ1[1:0]InputBIST mode request signal, one per processor.
MBISTCFG1[1:0]InputMBIST configuration.
MBISTADDR1[13:0]InputMBIST address.
MBISTINDATA1[63:0]InputMBIST data in.
MBISTOUTDATA1[63:0]OutputMBIST data out.
MBISTWRITEEN1InputGlobal write enable.
MBISTREADEN1InputGlobal read enable.
MBISTARRAY1[5:0]InputMBIST arrays used for testing RAMs.

MBISTBE1[63:0]

InputMBIST bit-write enable.

Table A.42 shows the L1 and DTCM signals for designs with ECC.

Table A.42. L1 and DTCM Cortex-R7 MBIST interface width with ECC

NameTypeSource/destinationDescription
MBISTACK1[1:0]OutputMBIST controller

BIST mode acknowledge signal:

0

Enabled.

1

Not enabled.

MBISTREQ1[1:0]InputBIST mode request signal, one per processor.
MBISTCFG1[1:0]InputMBIST configuration.
MBISTADDR1[13:0]InputMBIST address.
MBISTINDATA1[77:0]InputMBIST data in.
MBISTOUTDATA1[77:0]OutputMBIST data out.
MBISTWRITEEN1InputGlobal write enable.
MBISTREADEN1InputGlobal read enable.
MBISTARRAY1[5:0]InputMBIST arrays used for testing RAMs.

MBISTBE1[77:0]

InputMBIST bit-write enable.

Table A.43 shows the ITCM signals for designs without ECC.

Table A.43. ITCM Cortex-R7 MBIST interface width without ECC

NameTypeSource/destinationDescription
MBISTACK2[1:0]OutputMBIST controller

BIST mode acknowledge signal:

0

Enabled.

1

Not enabled.

MBISTREQ2[1:0]InputBIST mode request signal.
MBISTCFG2[1:0]InputMBIST all mode support.
MBISTADDR2[11:0]InputMBIST address.
MBISTINDATA2[63:0]InputMBIST data in.
MBISTOUTDATA2[63:0]OutputMBIST data out.
MBISTWRITEEN2InputGlobal write enable.
MBISTREADEN2InputGlobal read enable.
MBISTARRAY2[4:0]InputMBIST arrays used for testing RAMs.
MBISTBE2InputMBIST bit-write enable.

Table A.44 shows the ITCM signals for designs with ECC.

Table A.44. ITCM Cortex-R7 MBIST interface width with ECC

NameTypeSource/destinationDescription
MBISTACK2[1:0]OutputMBIST controller

BIST mode acknowledge signal:

0

Enabled.

1

Not enabled.

MBISTREQ2[1:0]InputBIST mode request signal.
MBISTCFG2[1:0]InputMBIST all mode support.
MBISTADDR2[11:0]InputMBIST address.
MBISTINDATA2[71:0]InputMBIST data in.
MBISTOUTDATA2[71:0]OutputMBIST data out.
MBISTWRITEEN2InputGlobal write enable.
MBISTREADEN2InputGlobal read enable.
MBISTARRAY2[4:0]InputMBIST arrays used for testing RAMs.
MBISTBE2InputMBIST bit-write enable.

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