A.5. Configuration signals

Table A.4 shows the configuration signals.

Table A.4. Configuration signals

NameTypeSource/destinationDescription
AXIPARITYLEVEL[a]InputSystem configuration

Selects between odd and even parity for buses:

0

Even parity.

1

Odd parity.

CFGEND[N:0]Input

Individual processor endianness configuration.

Forces the EE bit in the CP15 c1 Control Register (SCTLR) to 1 at reset so that the processor boots with big-endian data handling:

0

EE bit is LOW.

1

EE bit is HIGH.

This input is only sampled during reset of the processor.

See System Control Register.

CFGNMFI[N:0]Input

Configuration of FIs to be nonmaskable:

0

Clear the NMFI bit in the CP15 c1 Control Register.

1

Set the NMFI bit in the CP15 c1 Control Register.

This input is only sampled during reset of the processor.

See System Control Register

CLUSTERID[3:0]Input

Value read in Cluster ID field, bits[11:8], of the Multiprocessor Affinity Register (MPIDR).

See Multiprocessor Affinity Register.

INITRAM0Input

Input present if TCM present for processor 0. It enables the processor 0 to boot from the Instruction TCM. This input, when tied HIGH, enables the instruction TCM on leaving reset.

See ITCM Region Register.

INITRAM1Input

Input present if TCM present for processor 1. It enables the processor 1 to boot from the Instruction TCM. This input, when tied HIGH, enables the instruction TCM on leaving reset.

See ITCM Region Register.

MFILTERENInput

For use with configurations with two master ports.

It enables filtering of address ranges at reset for AXI Master port 1. This signal is sampled on exit from reset and sets the default value of the MFILTEREN bit in the SCU Control Register. See SCU Control Register.

0

Address filtering off.

1

Address filtering on.

See SCU Control Register and AXI master port 1.

MFILTEREND[11:0]Input

For use with configurations with two master ports.

Specifies the end address for address filtering at reset on AXI master port 1.

See SCU Control Register and AXI master port 1.

MFILTERSTART[11:0]InputSystem configuration

For use with configurations with two master ports.

Specifies the start address for address filtering at reset on AXI master port 1.

See SCU Control Register and AXI master port 1.

PERIPHBASE[31:13]Input

Specifies the base address for timers, watchdogs, interrupt controller, and SCU registers. Only accessible with memory-mapped accesses.

This value can be retrieved by a processor using the Configuration Base Address Register. See Configuration Base Address Register.

Note

This address must be in the range defined by PFILTERSTART[31:20] and PFILTEREND[31:20].

PFILTEREND[11:0] Input

For use with configurations with the AXI Master peripheral port.

Specifies the end address for address filtering at reset on the AXI peripheral port.

See AXI peripheral port .

PFILTERSTART[11:0]Input

For use with configurations with the AXI Master peripheral port.

Specifies the start address for address filtering at reset on the AXI peripheral port.

See AXI peripheral port .

SMPnAMP[N:0]OutputSystem integrity controller

Indicates AMP or SMP mode for each processor:

0

Asymmetric.

1

Symmetric.

This output reflects the value of ACTLR.SMP.

See Auxiliary Control Register.

TEINIT[N:0]InputSystem configuration

Individual processor out-of-reset default exception handling state:

0

ARM.

1

Thumb.

This input is only sampled during reset of the processor. It sets the initial value of SCTLR.TE.

See System Control Register.

VINITHI[N:0]Input

Individual processor control of the location of the exception vectors at reset:

0

Exception vectors start at address 0x00000000.

1

Exception vectors start at address 0xFFFF0000.[b]

This input is only sampled during reset of the processor. It sets the initial value of SCTLR.V.

See System Control Register and ITCM Region Register.

[a] Only present if bus ECC is selected. This is a build option.

[b] HIVECS == 1 is deprecated in PMSAv7.


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