9.3.11. SCU Error Bank Second Entry Register

The SCU Error Bank Second Entry Register characteristics are:

Purpose

Shows the second SCU error bank entry.

Usage constraints

There are no usage constraints.

Configurations

Available only in configurations where ECC is implemented.

Attributes

See the register summary in Table 9.2.

Figure 9.12 shows the SCU Error Bank Second Entry Register bit assignments.

Figure 9.12. SCU Error Bank Second Entry Register bit assignments

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Table 9.13 shows the SCU Error Bank Second Entry Register bit assignments.

Table 9.13. SCU Error Bank Second Entry Register bit assignments

BitsNameFunction
[31:24]ReservedSBZ
[23:16]WaysWays in the SCU tag ram, four bits per processor.
[15:14]ReservedSBZ
[13:5]IndexIndex in the SCU tag RAM.
[4:2]ReservedSBZ
[1:0]Status

Error status. The values are:

0b00

No error.

0b01

Error seen by SCU tag RAM, but not handled by processor.

0b10

Error seen by both SCU and processor.

0b11

Error is confirmed by software.


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