11.6.2. ACP limitations

The ACP is optimized for cache-line length transfers and supports a wide range of AMBA 3 AXI3 requests, but it has some limitations that must be considered:

ACP performance limitations

ACP accesses are optimized for transfers that match Cortex-R7 MPCore processor coherent requests:

  • A wrapped burst of four doublewords (length = 3, size = 3), with a 64-bit aligned address, and all byte strobes set.

  • An incremental burst of four doublewords, with the first address corresponding to the start of a cache line, and all byte strobes set.

For maximum performance use ACP accesses that match this optimized format. ACP accesses that do not match this format cannot benefit from the SCU optimizations, and have significantly lower performance. See ACP bridge for more information.

ACP functional limitations

The ACP is a full AMBA3 slave component, with the exception of the following transfers that are not supported:

  • Exclusive read and write transactions to coherent memory.

  • Locked read and write transactions to coherent memory.

  • Optimized coherent read and write transfers when byte strobes are not all set.

Because of this, it is not possible to use the LDREX/STREX mechanism through the ACP to gain exclusive access to coherent memory regions that are marked with AxUSER[0] = 1 and AxCACHE[1] = 1.

However, the LDREX/STREX mechanism is fully supported through the ACP for non-coherent memory regions, marked with AxUSER[0] = 0 or AxCACHE[1] =0.

See ACP bridge for more information on access support.

64-bit accesses to the AXI peripheral port always abort. 32-bit wide normal memory non-cacheable accesses from the ACP to the AXI peripheral port do not abort. See AXI peripheral port for more information.

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