A.4. Interrupt controller signals

Table A.3 shows the interrupt controller signals.

Table A.3. Interrupt controller signals

NameTypeSource/destinationDescription
IRQS[x:0]InputInterrupt sources

Interrupt distributor interrupt lines.

x can be 31, 63,…, up to 479 in increments of 32. If there are no interrupt lines, this input is removed.

nFIQ[N:0]Input

Individual processor legacy FIQ request input lines. Active-LOW interrupt request:

0

Active interrupt.

1

Do not activate interrupt.

The processor treats the nFIQ input as level sensitive. The nFIQ input must be asserted until the processor acknowledges the interrupt.

nFIQOUT[N:0]OutputPower controllerActive-LOW FIQ outputs from the internal GIC to processor 1 and processor 0 as appropriate. These indicate when interrupts are being forwarded to the processor.
nIRQ[N:0]InputInterrupt sources

Individual processor legacy IRQ request input lines. Active-LOW interrupt request:

0

Active interrupt.

1

Do not activate interrupt.

The processor treats the nIRQ input as level sensitive. The nIRQ input must be asserted until the processor acknowledges the interrupt.

nIRQOUT[N:0]OutputPower controller

Active-LOW IRQ outputs from the internal GIC to processor 1 and processor 0 as appropriate. These indicate when interrupts are being forwarded to the processor.


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