A.16. Memory reconstruction port signals

Table A.53 shows the MRP signals. x in the signal name represents either processor 0 or processor 1.

Table A.53. Memory reconstruction port signals

NameTypeSource/destinationDescription
MRPREADYxInputTrace analysis engineReady signal of any write access
MRPVALIDxOutputValid signal of any write access
MRPADDRx[31:0]OutputAddress of any write access
MRPDATAx[63:0]OutputData of any write access
MRPSTRBx[7:0]OutputStrobe of any write access

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