7.2.3. ECC on RAMs

This section describes the use of ECC on the RAMs in:

RAM targeted

To prevent the loss of any data that might cause the processor or the system to malfunction, the ECC protects the following:

  • L1 data cache RAMs.

  • L1 instruction cache RAMs.

  • SCU Tag RAM.

  • Instruction TCM.

  • Data TCM.

For more information on the RAM targeted and the level of fault detection support, see RAM protection summary.

Basic scheme

The basic ECC scheme for the L1 cache, SCU RAM, and TCM is as follows:

  • Any error, either soft or hard, is indicated to the system.

  • Any error detected is stored in an error bank, waiting to be analyzed by the system, and preventing that location from being used.

  • The system analyzes the faulty RAM location to check the full RAM space (MBIST). See Analysis of errors.

  • The processor can also analyze the faulty RAM location to check a single location or a range of locations (CP15 operation).

  • From the analysis, the errors detected are classified as soft or hard errors. If the errors are hard, the processor updates the error bank with this information and the corresponding RAM location is not used by subsequent accesses. There is one error bank for each of the following:

    • L1 data cache RAMs.

    • L1 instruction cache RAMs.

    • SCU Tag RAM.

    • Instruction TCM.

    • Data TCM.

Table 7.2 shows the basic scheme, and also the differences where it is part of the processor, that is, L1 cache and TCM, or is seen as a peripheral such as the SCU.

Table 7.2. Basic ECC scheme per RAM type

DescriptionL1 cacheSCUTCM
Correctable error notification to the system, bits[10:9] of the ACTLR cleared---
Correctable error notification to the system, bits[10:9] of the ACTLR setError notification[a]-Error notification[a]
Uncorrectable error notification to the systemError notification[a]Error notification[a]Error notification[a]
Logging of errorsUp to three entries in the error bankUp to two entries in the error bankOne entry in the error bank
Direct access to the faulty RAM location by the system for full RAM analysisMBISTMBISTMBIST or slave port
Direct access to the faulty RAM location by the processor itself for single location analysisCP15 Debug Cache Access RegistersMemory-mapped register in the SCUCP15 Debug TCM Access Registers
Access to the error bank to update it after analysis of the faulty RAM locationCP15Memory-mapped register in the SCUCP15

[a] Fault detection error notification is done by the primary output pins. See Error detection notification signals.


Auto-check mechanism

The direct access to the faulty RAM location by the processor for single location analysis also enables errors to be injected so that the error handling mechanism can be checked. This provides a full software support to generate errors on particular locations in the RAM, and then enabling and disabling the ECC after those accesses. See SCU Debug tag RAM access and Cache and TCM Debug Operation Register for more information.

MBIST for full RAM analysis

The MBIST interface can be used during WFI. The MBIST controller has some arbitration on the RAMs and can get a clock running in the processor clock module when the MBISTENABLE signal is active, so that flops before and after the RAMs can be activated. Any other MBIST usage while the processor is running is not supported.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814