A.3. Reset signals

Table A.2 shows the reset signals.

Table A.2. Reset signals

NameTypeSource/destinationDescription
nCPURESET[N:0]InputReset controllerIndividual processor resets.
nCPUHALT[N:0]Input

Individual processor input.

It can be asserted while the processor is in reset to stop the processor from fetching and executing instructions after coming out of reset. While the processor is halted in this way, the TCMs can be preloaded with the appropriate data.

When it is deasserted, the processor starts fetching instructions from the reset vector address in the normal way.

nDBGRESET[N:0]InputProcessor debug logic resets.
nPERIPHRESETInputTimer and interrupt controller reset.
nSCURESETInputSCU global reset.
nCTRESETInputReset for CoreSight debug logic, that is, CTI0, CTI1, CTM, and ROM table.
nETM0RESETInputReset for ETM0, if present.
nETM1RESETInputReset for ETM1, if present.
nWDRESET[N:0]InputProcessor watchdog resets.
WDRESETREQ[N:0]OutputProcessor watchdog reset requests.

See Resets.

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