9.3.1. SCU Control Register

The SCU Control Register characteristics are:

Purpose

Enables:

  • Speculative linefills to L2 with the L2C-310 Cache Controller.

  • IC standby mode.

  • SCU standby mode.

  • SCU tag RAM ECC support.

  • Address filtering.

  • Bus ECC and parity control.

  • Access control on master ports.

  • Cache coherency features.

Usage constraints

This register is writable if the relevant bit in the SAC register is set.

Configurations

Available in all Cortex-R7 MPCore configurations.

Attributes

See the register summary in Table 9.2.

Figure 9.2 shows the SCU Control Register bit assignments.

Figure 9.2. SCU Control Register bit assignments

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Table 9.3 shows the SCU Control Register bit assignments.

Table 9.3. SCU Control Register bit assignments

Bits NameDescription
[31:16]ReservedSBZ
[15]ECC check enable on ACPWhen set, enables ECC check on the Accelerator Coherency Port (ACP).
[14]ECC check enable on MPWhen set, enables ECC check on the AXI master peripheral port..
[13]ECC check enable on M1When set, enables ECC check on AXI master port 1.
[12]ECC check enable on M0When set, enables ECC check on AXI master port 0.
[11:7]ReservedSBZ
[6]IC standby enableWhen set, this stops the interrupt controller clock when no interrupts are pending, and neither processor is performing a read/write request.
[5]SCU standby enable

When set, the clock in the SCU is turned off when all processors are in WFI mode or in powerdown, there is no pending request on the ACP, if implemented, and there is no remaining activity in the SCU.

When the clock in the SCU is off, ARREADYS, AWREADYS, and WREADYS on the ACP are forced LOW. The clock is turned on when any processor leaves WFI mode, or if there is a new request on the ACP.

[4]ReservedSBZ
[3]SCU speculative linefills enable

When set, coherent linefill requests are sent speculatively to the L2C-310 Cache Controller in parallel with the tag look-up.

If the tag look-up misses, the confirmed linefill is sent to the L2C-310 Cache Controller and receives RDATA earlier because the data request was already initiated by the speculative request. This feature works only if there is an L2C-310 Cache Controller in the design. When filtering is enabled only port 0 can receive speculative linefills.

[2]SCU RAMs ECC enable

Enables ECC:

1

ECC on.

0

ECC off. This is the default setting.

This bit is always zero if support for ECC is not implemented.

[1]Address filtering enable

This is a read-only bit that indicates address filtering:

1

Address filtering on.

0

Address filtering off.

This value is the value of MFILTEREN sampled when nSCURESET is deasserted.

This bit is always zero if the SCU is implemented in the single master port configuration. See AXI master port 1.

[0]SCU enable

Enables SCU:

1

SCU enabled.

0

SCU disabled. This is the default setting.


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