A.11.5. Bus ECC error signals on AXI slave ports

Table A.38 shows the bus ECC error signals on the AXI slave ports. These signals are only present if ECC is implemented.

Table A.38. Bus ECC error signals on AXI slave ports

NameTypeSource/destinationDescription
AXICORRERRSCOutputAXI ACPCorrectable error on DW channel of AXI ACP port
AXIFATALERRSC[4:0]Output

Fatal error on AXI ACP port:

[4] fatal error on DR channel.

[3] fatal error on AR channel.

[2] fatal error on DB channel.

[1] fatal error on DW channel.

[0] fatal error on AW channel.

ARVALIDPTYSCInputParity for address valid.
ARREADYPTYSCOutputAXI ACPParity for address ready.
ARADDRPTYSC[3:0]InputParity for address.
ARCTLPTYSC[3:0]Input

Parity signals:

[0] parity for address ID.

[1] parity for burst length.

[2] parity for burst size, burst type, and lock type.

[3] parity for cache type and protection.

ARUSERPTYSCInputParity for transfer attributes.
RVALIDPTYSCOutputParity for read valid.
RREADYPTYSCInputParity for read ready.
RCTLPTYSC[1:0]Output

Parity signals:

[0] parity for read ID.

[1] parity for read response.

RDATAERRCODESC[7:0]OutputECC bits on data bus, when BUS_ECC build parameter is set.
AWVALIDPTYSCInputParity for address valid.
AWREADYPTYSCOutputParity for address ready.
AWADDRPTYSC[3:0]InputParity for address.
AWCTLPTYSC[3:0]Input

Parity signals:

[0] parity for address ID.

[1] parity for burst length.

[2] parity for burst size, burst type, and lock type.

[3] parity for cache type and protection.

AWUSERPTYSCInput Parity for transfer attributes.
WVALIDPTYSCInput Parity for write valid.
WREADYPTYSCOutputParity for write ready.
WCTLPTYSC[2:0]Input

Parity signals:

[0] parity for write ID.

[1] parity for write strobes.

[2] parity for write last.

  
WDATAERRCODESC[7:0]InputECC bits on data bus, when BUS_ECC build parameter is set.
BVALIDPTYSCOutputParity for response valid.
BREADYPTYSCInputParity for response ready.
BCTLPTYSC[1:0]Output

Parity signals:

[0] parity for response ID.

[1] parity for write response.


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