9.3.8. Peripherals Filtering End Address Register

The Peripherals Filtering End Address Register characteristics are:

Purpose

Provides the filtering end address for the peripheral port.

Usage constraints

This register is read-only. It has an inclusive address as its end address. This means that the topmost megabyte of address space of memory can be included in the filtering address range. For the peripheral port region to operate, the filtering start address must be lower than the filtering end address.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.2.

Figure 9.9 shows the Peripherals Filtering End Address Register bit assignments.

Figure 9.9. Peripherals Filtering End Address Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 9.10 shows the Peripherals Filtering End Address Register bit assignments.

Table 9.10. Peripherals Filtering End Address Register bit assignments

Bits Name Description
[31:20]Filtering end address

Filtering end address for the peripheral port.

The default value is the value of PFILTEREND sampled on exit from reset. The value on the input gives the upper address bits with 1MB granularity.

[19:0]ReservedSBZ

See Configuration signals. See also AXI peripheral port .

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814