9.3.12. SCU Debug tag RAM access

You can access a specific faulty location in a Tag RAM or inject fake errors to check the ECC mechanism in the SCU. Three SCU registers are provided:

Accessing an SCU tag RAM location

To read a given SCU tag RAM location:

To write a given SCU tag RAM location:

SCU Debug Tag RAM Operation Register

The SCU Debug Tag RAM Operation Register characteristics are:

Purpose

Gives the address and action for SCU tag RAM direct access.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.2.

Figure 9.13 shows the SCU Debug Tag RAM Operation Register bit assignments.

Figure 9.13. SCU Debug Tag RAM Operation Register bit assignments

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Table 9.14 shows the SCU Debug Tag RAM Operation Register bit assignments.

Table 9.14. SCU Debug Tag RAM Operation Register bit assignments

BitsNameFunction
[31:30]SCU tag RAM way target

Indicates the number of the RAM way.

[29:25]ReservedSBZ
[24]SCU tag RAM processor target

Indicates the processor target:

0

Processor 0.

1

Processor 1.

[23:14]ReservedSBZ
[13:5]SCU tag RAM set targetIndex to read or write the SCU tag RAM.
[4:1]ReservedSBZ
[0]Read or write operation

Specifies whether it is a read or write operation:

0

Read.

1

Write.


SCU Debug Tag RAM Data Value Register

The SCU Debug Tag RAM Data Value Register characteristics are:

Purpose

Gives the data value for SCU tag RAM direct access.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.2.

Figure 9.14 shows the SCU Debug Tag RAM Data Value Register bit assignments.

Figure 9.14. SCU Debug Tag RAM Data Value Register bit assignments

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Table 9.15 shows the SCU Debug Tag RAM Data Value Register bit assignments.

Table 9.15. SCU Debug Tag RAM Data Value Register bit assignments

BitsNameFunction
[31:23]ReservedSBZ
[22]ValidValid bit.
[21:17]Value

Tag value:

[21]

4K.

[21:20]

8K.

[21:19]

16K.

[21:18]

32K.

[21:17]

64K.

Unused bits are Reserved.

[16:0]ReservedSBZ

SCU Debug Tag RAM ECC Chunk Register

The SCU Debug Tag RAM ECC Chunk Register characteristics are:

Purpose

Shows the ECC chunk value.

Usage constraints

There are no usage constraints.

Configurations

Available only in configurations where ECC is implemented.

Attributes

See the register summary in Table 9.2.

Figure 9.15 shows the SCU Debug Tag RAM ECC Chunk Register bit assignments.

Figure 9.15. SCU Debug Tag RAM ECC Chunk Register bit assignments

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Table 9.16 shows the SCU Debug Tag RAM ECC Chunk Register bit assignments.

Table 9.16. SCU Debug Tag RAM ECC Chunk Register bit assignments

BitsNameFunction
[31:7]-SBZ
[6:0]ChunkECC chunk value

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