A.8.4. AXI TCM slave port signals

Table A.26 shows the AXI TCM slave port clock enable signal.

Table A.26. AXI TCM slave port clock enable signal

NameTypeSource/destinationDescription
ACLKENSTInputClock controller

Clock bus enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock.


Table A.27 shows the AXI TCM slave port read address signals.

Table A.27. AXI TCM slave port read address signals

NameTypeSource/destinationDescription
ARVALIDSTInputAXI3 deviceAddress valid
ARREADYSTOutputAddress ready
ARIDST[n][a]InputAddress ID.
ARADDRST[16:0]InputAddress
ARSIZEST[1:0]InputBurst size
ARLENST[3:0]InputBurst length
ARBURSTST[1:0]InputBurst type
ARUSERST[1:0]InputTransfer attributes

[a] You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.


Table A.28 shows the AXI TCM slave port read data signals.

Table A.28. AXI TCM slave port read data signals

NameTypeSource/destinationDescription
RVALIDSTOutputAXI3 deviceRead valid
RREADYSTInputRead ready
RIDST[n][a]OutputRead ID
RLASTSTOutputRead last
RDATAST[63:0]OutputRead data
RRESPST[1:0]OutputRead response

[a] You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.


Table A.29 shows the AXI TCM slave port write address signals.

Table A.29. AXI TCM slave port write address signals

NameTypeSource/destinationDescription
AWVALIDSTInputAXI3 deviceAddress valid.
AWREADYSTOutputAddress ready.
AWIDST[n][a]InputAddress ID.
AWADDRST[16:0]InputAddress.
AWSIZEST[1:0]InputBurst size.
AWLENST[3:0]InputBurst length. The maximum burst transfer must correspond to an L1 cache line, that is, 256 bits.
AWBURSTST[1:0]InputBurst type.
AWUSERST[1:0]InputTransfer attributes.

[a] You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.


Table A.30 shows the AXI TCM slave port write data signals.

Table A.30. AXI TCM slave port write data signals

NameTypeSource/destinationDescription
WVALIDSTInputAXI3 deviceWrite valid
WREADYSTOutputWrite ready
WIDST[n][a]InputWrite ID
WLASTSTInputWrite last
WSTRBST[7:0]InputWrite strobes
WDATAST[63:0]InputWrite data

[a] You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.


Table A.31 shows the AXI TCM slave port write response signals.

Table A.31. AXI TCM slave port write response signals

NameTypeSource/destinationDescription
BVALIDSTOutputAXI3 deviceResponse valid
BREADYSTInputResponse ready
BIDST[n][a]OutputResponse ID
BRESPST[1:0]OutputWrite response

[a] You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.


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