9.3.2. SCU Configuration Register

The SCU Configuration Register characteristics are:

Purpose
  • Reads tag RAM sizes for the Cortex-R7 processors that are present.

  • Determines the Cortex-R7 processors that are taking part in coherency.

  • Reads the number of Cortex-R7 processors present.

Usage constraints

This register is read-only.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.2.

Figure 9.3 shows the SCU Configuration Register bit assignments.

Figure 9.3. SCU Configuration Register bit assignments

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Table 9.4 shows the SCU Configuration Register bit assignments.

Table 9.4. SCU Configuration Register bit assignments

BitsNameDescription
[31:16]ReservedSBZ
[15:12] Cache size for processor 1

The encoding is as follows:

0b0101

64KB cache.

0b0100

32KB cache.

0b0011

16KB cache.

0b0010

8KB cache.

0b0001

4KB cache.

0b0000

0KB cache.

All other values are Reserved.

[11:8] Cache size for processor 0

The encoding is as follows:

0b0101

64KB cache.

0b0100

32KB cache.

0b0011

16KB cache.

0b0010

8KB cache.

0b0001

4KB cache.

0b0000

0KB cache.

All other values are Reserved.

[7:6]ReservedSBZ
[5:4]Processors in coherency mode

Shows the Cortex-R7 processors that are in Symmetric Multi-processing (SMP) or Asymmetric Multi-processing (AMP) mode:

1

This Cortex-R7 processor is in SMP mode taking part in coherency.

0

This Cortex-R7 processor is in AMP mode not taking part in coherency or not present.

Bit 5 is for processor 1

Bit 4 is for processor 0.

[3:1]ReservedSBZ
[0]Number of processors

Number of processors present in the Cortex-R7 MPCore processor:

1

Two Cortex-R7 processors, processor 0 and processor 1.

0

One Cortex-R7 processor, processor 0.


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