A.14. External debug signals

Table A.45 shows the debug enable signals.

Table A.45. Debug enable signals

NameTypeSource/destinationDescription
DBGEN[N:0]InputExternal debug device

Individual processor invasive debug enable:

0

Not enabled.

1

Enabled.

NIDEN[N:0]Input

Individual processor noninvasive debug enable:

0

Not enabled.

1

Enabled.


Table A.46 shows the debug signals.

Table A.46. Debug signals

NameTypeSource/destinationDescription
EDBGRQ[N:0]InputExternal debug device

Individual processor external debug request:

0

No external debug request

1

External debug request.

The processor treats the EDBGRQ input as level sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGACK[N:0]OutputIndividual processor debug acknowledge signal. Acknowledges that the corresponding processor has entered debug state after an external debug request.
DBGCPUDONE[N:0]OutputAcknowledges that corresponding processor has entered debug state and that all previous non-debug state memory accesses are complete.
DBGRESTART[N:0]Input

Individual processor signal that causes the processor to exit debug state. It must be held HIGH until DBGRESTARTED is deasserted:

0

Not enabled.

1

Enabled.

DBGRESTARTED[N:0]Output

Individual processor signal. Used with DBGRESTART to move from debug state to normal state:

0

Not enabled.

1

Enabled.

DBGNOPWRDWN[N:0]OutputOutput reflecting the value of DBGPRCR[0]. See the ARM Architecture Reference Manual.
DBGSWENABLE[N:0]Input

When LOW only the external debug agent can modify debug registers:

0

Not enabled.

1

Enabled. Access by the software through the extended CP14 interface is permitted. External CP14 and external debug accesses are permitted.

DBGROMADDR[31:12]InputExternal debug device

CoreSight System configuration. Specifies bits[31:12] of the ROM table physical address.

If the address cannot be determined, tie this signal off to zero.

DBGROMADDRVInput

Valid signal for DBGROMADDR.

If the address cannot be determined, tie this signal LOW.

DBGSELFADDR[31:17]Input

Specifies bits[31:17] of the two’s complement signed offset from the ROM Table physical address to the physical address where the debug registers are memory-mapped.

If the offset cannot be determined, tie this signal off to zero.

DBGSELFADDRVInput

Valid signal for DBGSELFADDR.

If the offset cannot be determined, tie this signal LOW.


Table A.47 shows the miscellaneous debug signals.

Table A.47. Miscellaneous debug signals

NameTypeSource/destinationDescription
COMMRX[N:0]OutputExternal debug device

Individual processor signal. Comms Channels Receive portion of Data Transfer Register full flag:

0

Empty.

1

Full.

COMMTX[N:0]Output

Individual processor signal. Comms Channels Transmit portion of Data Transfer Register full flag:

0

Empty.

1

Full.


Table A.48 shows the Debug APB interface signals.

Table A.48. Debug APB interface signals

NameTypeSource/destinationDescription
PENABLEDBGInputCoreSight APB devicesAPB clock enable. Indicates a second and subsequent cycle of a transfer.
PRDATADBG[31:0]OutputAPB read data bus.
PSELDBGInput

Debug registers select:

0

Debug registers not selected.

1

Debug registers selected.

PSLVERRDBGOutput

APB slave error signal:

0

No transfer error.

1

Transfer error.

PWRITEDBGInputAPB read/write signal.
PADDRDBG[16:2]InputCoreSight APB devices

Programming address. Bits[16:12] have the following meaning:

00000

ROM table.

10000

Processor 0 debug.

10001

Processor 0 PMU.

10010

Processor 1 debug, if processor 1 is present, otherwise reserved.

10011

Processor 1 PMU, if processor 1 is present, otherwise reserved.

11000

CTI0

11001

CTI1, if processor 1 is present, otherwise reserved.

11100

ETM0

11101

ETM1, if ETM1 is present, otherwise reserved.

PADDRDBG31Input

APB address bus bit[31]:

0

Not an external debugger access.

1

External debugger access.

PREADYDBGOutput

APB slave ready. An APB slave can assert PREADY to extend a transfer.

PWDATADBG[31:0]InputAPB write data.

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