A.2. Clock and control signals

Table A.1 shows the clock and clock control signals.

Table A.1. Clock and clock control signals

NameTypeSource/destinationDescription
CLKInputClock controllerGlobal clock.
CPUCLKOFF[N:0][a]InputReset controller

Individual processor clock control, active-LOW:

0

Clock is enabled.

1

Clock is stopped.

This includes the FPU if it is present.

DBGCLKOFF[N:0][a]Input

Individual processor debug clock control, active-LOW:

0

Processor debug clock is enabled.

1

Processor debug clock is stopped.

DUALPERIPHCLK[b]InputClock controllerClock for dual SCU.
DUALPERIPHCLKEN[b]InputReset controllerClock enable for dual SCU and peripheral interface signals.
DUALPERIPHCLKOFF[a][b]InputIndividual processor clock control for timer, watchdog, and interrupt controller of dual SCU.
PERIPHCLKInputClock controllerClock for the timer, watchdog, and interrupt controller.
PERIPHCLKENInputReset controllerClock enable for SCU and peripheral interface signals.
PERIPHCLKOFF[a][b]InputIndividual processor clock control for timer, watchdog, and interrupt controller of SCU.
SCUCLKOFF[a][b]InputClock control delay for dual SCU.
CTCLKOFF[a]InputUsed to control the CoreSight debug logic clock, that is, CTI0, CTI1, CTM, and ROM table.
ETM0CLKOFF[a]InputUsed to control the ETM0 clock, if ETM0 is present.
ETM1CLKOFF[a]InputUsed to control the ETM1 clock, if ETM1 is present.

[a] Used to deassert the reset synchronously when leaving reset, but not used for clock enable.

[b] Only present if lock-step or split/lock is implemented. Figure A.1 shows how these signals are used in a single SCU and a dual SCU implementation.


Figure A.1. Clocking in lock-step or split/lock implementation

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See Clocking, resets, and initialization.

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