A.11.3. Bus ECC error signals on AXI master ports

Table A.36 shows the bus ECC error signals on the AXI master ports. These signals are only present if ECC is implemented. x in the signal name represents either AXI Master Port 0 or AXI Master Port 1.

Table A.36. Bus ECC error signals on AXI master ports

NameTypeSource/destinationDescription
AXICORRERRMxOutputAXI master portCorrectable error on DR channel of AXI master port.
AXIFATALERRMx[4:0]Output

Fatal error on AXI master port:

[4] fatal error on DR channel.

[3] fatal error on AR channel.

[2] fatal error on DB channel.

[1] fatal error on DW channel.

[0] fatal error on AW channel.

ARVALIDPTYMxOutputParity for address valid.
ARREADYPTYMxInputParity for address ready.
ARADDRPTYMx[3:0]OutputParity for address.
ARCTLPTYMx[3:0]Output

Parity signals:

[0] parity for address ID.

[1] parity for burst length.

[2] parity for burst size, burst type, and lock type.

[3] parity for cache type and protection.

ARUSERPTYMxOutputParity for transfer attributes.
RVALIDPTYMxInputParity for read valid.
RREADYPTYMxOutputParity for read ready.
RCTLPTYMx[1:0]Input

Parity signals:

[0] parity for read ID.

[1] parity for read response and read last.

RDATAERRCODEMx[7:0]InputECC bits on data bus, when BUS_ECC build parameter is set.
AWVALIDPTYMxOutputParity for address valid.
AWREADYPTYMxInputParity for address ready.
AWADDRPTYMx[3:0]OutputParity for address.
AWCTLPTYMx[3:0]Output

Parity signals:

[0] parity for address ID.

[1] parity for burst length.

[2] parity for burst size, burst type, and lock type.

[3] parity for cache type and protection.

AWUSERPTYMxOutput Parity for transfer attributes.
WVALIDPTYMxOutput Parity for write valid.
WREADYPTYMxInputParity for write ready.
WCTLPTYMx[2:0]OutputAXI master port

Parity signals:

[0] parity for write ID.

[1] parity for write strobes.

[2] parity for write last.

WUSERPTYMxOutputParity for transfer attributes.
WDATAERRCODEMx[7:0]OutputECC bits on data bus, when BUS_ECC build parameter is set.
BVALIDPTYMxInputParity for response valid.
BREADYPTYMxOutputParity for response ready.
BCTLPTYMx[1:0]Input

Parity signals:

[0] parity for response ID.

[1] parity for write response.


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