A.8.3. AXI ACP slave port signals

Table A.20 shows the AXI ACP slave port clock enable signal.

Table A.20. AXI ACP slave port clock enable signal

NameTypeSource/destinationDescription
ACLKENSCInputClock controller

Clock bus enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock.


Table A.21 shows the AXI ACP slave port read address signals.

Table A.21. AXI ACP slave port read address signals

NameTypeSource/destinationDescription
ARVALIDSCInputAXI3 deviceAddress valid.
ARREADYSCOutputAddress ready.
ARIDSC[n][a]InputAddress ID.
ARADDRSC[31:0]InputAddress.
ARSIZESC[1:0]InputBurst size.
ARLENSC[3:0]InputBurst length.
ARBURSTSC[1:0]InputBurst type.
ARCACHESC[3:0]InputCache type.
ARPROTSC[2:0]InputProtection type.
ARLOCKSCInputLock type.
ARUSERSC[4:0]InputTransfer attributes.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter.


Table A.22 shows the AXI ACP slave port read data signals.

Table A.22. AXI ACP slave port read data signals

NameTypeSource/destinationDescription
RVALIDSCOutputAXI3 deviceRead valid.
RREADYSCInputRead ready.
RIDSC[n][a]OutputRead ID.
RLASTSCOutputRead last.
RDATASC[63:0]OutputRead data.
RRESPSC[1:0]OutputRead response.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter.


Table A.23 shows the AXI ACP slave port write address signals.

Table A.23. AXI ACP slave port write address signals

NameTypeSource/destinationDescription
AWVALIDSCInputAXI3 deviceAddress valid.
AWREADYSCOutputAddress ready.
AWIDSC[n][a]InputAddress ID.
AWADDRSC[31:0]InputAddress.
AWSIZESC[1:0]InputBurst size.
AWLENSC[3:0]InputBurst length. The maximum burst transfer must correspond to an L1 cache line, that is, 256 bits.
AWBURSTSC[1:0]InputBurst type.
AWCACHESC[3:0]InputCache type.
AWPROTSC[2:0]InputProtection type.
AWLOCKSCInputLock type.
AWUSERSC[5:0]InputTransfer attributes.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter.


Table A.24 shows the AXI ACP slave port write data signals.

Table A.24. AXI ACP slave port write data signals

NameTypeSource/destinationDescription
WVALIDSCInputAXI3 deviceWrite valid.
WREADYSCOutputWrite ready.
WIDSC[n][a]InputWrite ID.
WLASTSCInputAXI3 deviceWrite last.
WSTRBSC[7:0]InputWrite strobes.
WDATASC[63:0]InputWrite data.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter.


Table A.25 shows the AXI ACP slave port write response signals.

Table A.25. AXI ACP slave port write response signals

NameTypeSource/destinationDescription
BVALIDSCOutputAXI3 deviceResponse valid.
BREADYSCInputResponse ready.
BIDSC[n][a]OutputResponse ID.
BRESPSC[1:0]OutputWrite response.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter.


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