7.2.4. ECC on external AXI bus

All master buses, that is, AXI master port 0 and AXI master port 1, and the peripheral port, generate ECC check bits that are computed on all signals of the bus for write accesses, such as payload and control, including the AXI valid and AXI ready signals.

For read accesses, the complete bus is decoded:

An external write access must be decoded on the ACP:

An external read access encodes all signals of the bus, such as payload and control, including the AXI valid and AXI ready signals. For more information on ECC for the ACP, see ACP bridge.

Note

  • ECC is only present on data buses. All other signals are protected by parity.

  • ECC on the ACP bus is supported only when the ACP bridge is implemented.

  • For build options where the ECC on the external ACP bus is supported, when byte line strobes are sparse on an ACP write access, the unused bytes are masked in the processor and assumed to be driven LOW. This is because the ECC is computed on a 64-bit chunk. Therefore, a master driving the ACP must compute the ECC bits together with the write data with the same assumption.

The AXI slave port is not protected by ECC. It reports any ECC error as a slave error on the AXI bus.

If ECC errors are found on TCM RAMs:

You can configure whether this logic is present in the Cortex-R7 MPCore processor.

Note

To enable ECC in the Cortex-R7 MPCore processor, you must first enable ECC on the RAMs.

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