11.3. Accessing RAMs using the AXI3 interface

This section describes how to access the TCM RAMs using the AXI slave interface.

The Cortex-R7 MPCore processor has a single AXI slave port. The port is 64 bits wide and conforms to the AXI standard. Within the AXI standard, the slave port uses the AWUSERS and ARUSERS each as two separate chip select input signals to enable access to the TCMs as shown in Table 11.11.

Table 11.11. TCM accesses

AxUSERS[1:0] valueTCM
00Instruction TCM of processor 0
01Data TCM of processor 0
10Instruction TCM of processor 1
11Data TCM of processor 1.

The external AXI system must generate the chip select signals. The slave interface routes the access to the required RAM.

Table 11.12 shows the MSB bit for the different TCM RAM sizes.

Table 11.12. MSB bit for the different TCM RAM sizes


ARADDRS[16:3] indicates the address of the doubleword in the TCM that you want to access. If you are accessing a TCM that is smaller than the maximum 128KB, then it is possible to address a doubleword that is outside of the physical size of the TCM.

An access to the TCM RAMs is given a SLVERR error response if:

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