A.8.1. AXI master signals

x in the signal name represents either master 0, the primary AXI master, or master 1, the optional secondary AXI master.

Table A.8 shows the AXI master interface clock enable signals.

Table A.8. AXI master interface clock enable signals

NameTypeSource/destinationDescription
INCLKENMxInputCLK

Clock bus enable for the AXI bus that enables the AXI interface to operate at either:

  • Integer ratios of the system clock.

  • Half integer ratios of the system clock.

Inputs are sampled on rising edges of CLK only when INCLKENMx is HIGH.

OUTCLKENMxInput

Clock bus enable for the AXI bus that enables the AXI interface to operate at either:

  • Integer ratios of the system clock.

  • Half integer ratios of the system clock.

Outputs are updated on rising edges of CLK only when OUTCLKENMx is HIGH.


Table A.9 shows the AXI master read address signals.

Table A.9. AXI master read address signals

NameTypeSource/destinationDescription
ARADDRMx[31:0]OutputAXI3 deviceAddress.
ARBURSTMx[1:0]Output

Burst type:

0b1

INCR incrementing burst.

0b10

WRAP wrapping burst.

All other values are reserved.

ARCACHEMx[3:0]Output

Cache type giving additional information about cacheable characteristics.

ARIDMx[n][a]OutputRequest ID.
ARLENMx[3:0]OutputAXI3 device

The number of data transfers that can occur within each burst. Cacheable traffic generates transactions with four data transfers. For a description of other traffic, see Supported AXI3 transfers. Burst transactions from the ACP can be 1-16 transfers long.

0b0000

1 data transfer.

0b0001

2 data transfers.

0b0010

3 data transfers.

0b0011

4 data transfers.

0b0100

5 data transfers.

0b0101

6 data transfers.

0b0110

7 data transfers.

0b0111

8 data transfers.

0b1000

9 data transfers.

0b1001

10 data transfers.

0b1010

11 data transfers.

0b1011

12 data transfers.

0b1100

13 data transfers.

0b1101

14 data transfers.

0b1110

15 data transfers.

0b1111

16 data transfers.

ARLOCKMx[1:0]Output

Lock type:

0b00

Normal access.

0b01

Exclusive access.

0b10

Locked access.

ARPROTMx[2:0]OutputProtection type
ARREADYMxInputAddress ready
ARSIZEMx[1:0]Output

Burst size:

0b000

8-bit transfer.

0b001

16-bit transfer.

0b010

32-bit transfer.

0b011

64-bit transfer.

ARUSERMx[8:0]OutputTransfer attributes. See AXI3 USER bits.
ARVALIDMxOutputAddress valid.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.10 shows the AXI master read data signals.

Table A.10. AXI master read data signals

NameTypeSource/destinationDescription
RDATAMx[63:0]InputAXI3 deviceRead data
RDATAERRCODEMx[7:0]InputECC bits on data bus, when BUS_ECC build parameter is set
RIDMx[n][a]InputRead ID
RLASTMxInputRead last indication
RREADYMxOutputRead ready
RRESPMx[1:0]InputRead response
RVALIDMxInputRead valid
SRENDMx[3:0]InputSpeculative read information from optional L2 Cache Controller. See the CoreLink Level 2 Cache Controller (L2C-310) Technical Reference Manual for more information.
SRIDx[n][a]InputID for speculative reads returned by L2 Cache Controller

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.11 shows the AXI master write address signals.

Table A.11. AXI master write address signals

NameTypeSource/destinationDescription
AWADDRMx[31:0]OutputAXI3 deviceAddress
AWBURSTMx[1:0]Output

Burst type:

0b1

INCR incrementing burst.

0b10

WRAP wrapping burst.

All other values are reserved.

AWCACHEMx[3:0]OutputCache type giving additional information about cacheable characteristics.
AWIDMx[n][a]OutputWrite ID
AWLENMx[3:0]OutputAXI3 device

The number of data transfers that can occur within each burst.

For a description of other processor-generated traffic, see Supported AXI3 transfers. Burst transactions from the ACP can be 1-16 transfers long.

0b000

1 data transfer.

0b001

2 data transfers.

0b010

3 data transfers.

0b011

4 data transfers.

0b100

5 data transfers.

0b101

6 data transfers.

0b110

7 data transfers.

0b111

8 data transfers.

0b1000

9 data transfers.

0b1001

10 data transfers.

0b1010

11 data transfers.

0b1011

12 data transfers.

0b1100

13 data transfers.

0b1101

14 data transfers.

0b1110

15 data transfers.

0b1111

16 data transfers.

AWLOCKMx[1:0]Output

Lock type:

0b0

Normal access.

0b1

Exclusive access.

0b10

Locked access.

AWPROTMx[2:0]OutputProtection type
AWREADYMxInputAddress ready
AWSIZEMx[1:0]Output

Burst size:

0b00

8-bit transfer.

0b01

16-bit transfer.

0b10

32-bit transfer.

0b11

64-bit transfer.

AWUSERMx[10:0]OutputTransfer attributes. See AXI3 USER bits.
AWVALIDMxOutputAddress valid

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.12 shows the AXI master write data signals.

Table A.12. AXI master write data signals

NameTypeSource/destinationDescription
WDATAMx[63:0]OutputAXI3 deviceWrite data
WIDMx[n][a]OutputWrite ID
WLASTMxOutputWrite last indication
WREADYMxInputWrite ready
WSTRBMx[7:0]OutputWrite byte-lane strobe
WVALIDMxOutputWrite valid
WUSERMx[1:0]OutputTransfer attributes. See AXI3 USER bits.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.13 shows the AXI master write response signals.

Table A.13. AXI master write response signals

NameTypeSource/destinationDescription
BIDMx[n][a]InputL2C-310 or other system AXI3 devicesResponse ID
BREADYMxOutputResponse ready
BRESPMx[1:0]InputWrite response
BVALIDMxInputResponse valid

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


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