10.5.3. External debug interface

See External debug signals for a complete list of the external debug signals.

Figure 10.1 shows the external debug interface signals.

Figure 10.1. External debug interface signals

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Authentication signals

Table 10.13 shows a list of the valid combinations of authentication signals along with their associated debug permissions.

Table 10.13. Authentication signal restrictions

DBGENNIDENInvasive debug permittedNon-invasive debug permitted
00NoNo
01NoYes
10YesYes
11YesYes

Debug APB interface

The system can access memory-mapped debug registers through the Cortex-R7 MPCore APB slave port. This APB slave interface supports 32-bit wide data, stalls, and slave-generated aborts. Table 10.14 shows the mapping of PADRRDBG[16:2].

Table 10.14. PADDRDBG[16:2] mapping

Address map Reset domain Component
0x00000-0x00FFFIntegration ROM Table.
0x01000-0x0FFFF- Reserved.
0x10000-0x10FFFCPU0Processor 0 debug. See Table 10.8 for debug resource memory mapping.
0x11000-0x11FFFCPU0Processor 0 PMU. See Performance Monitoring Unit for PMU resource mapping.
0x12000-0x12FFFCPU1Processor 1 Debug. See Table 10.8 for debug resource memory mapping.
0x13000-0x13FFFCPU1Processor 1 PMU. See Performance Monitoring Unit for PMU resource mapping.
0x14000-0x17FFF-Reserved.
0x18000-0x18FFFIntegrationProcessor 0 CTI.
0x19000-0x19FFFIntegrationProcessor 1 CTI.
0x20000-0x1BFFF-Reserved.
0x1C000-0x1CFFFIntegration Processor 0 ETM.
0x1D000-0x1DFFFIntegration Processor 1 ETM.
0x1E000-0x1FFFF-Reserved.

The PADDRDBG31 signal indicates the source of the access to the processor.

External debug request interface

The following sections describe the external debug request interface signals:

EDBGRQ

This signal generates a halting debug event by requesting the processor to enter debug state. When this occurs, the DSCR[5:2] method of debug entry bits are set to 0b0100. When EDBGRQ is asserted, it must be held until DBGACK is asserted. Failure to do so causes unpredictable behavior of the processor.

DBGACK

The processor asserts DBGACK to indicate that the system has entered debug state. It serves as a handshake for the EDBGRQ signal. The DBGACK signal is also driven HIGH when the debugger sets the DSCR[10] DbgAck bit to 1.

DBGCPUDONE

DBGCPUDONE is asserted when the processor has completed a Data Synchronization Barrier (DSB) as part of the entry procedure to debug state.

The processor asserts DBGCPUDONE only after it has completed all Non-debug state memory accesses. Therefore the system can use DBGCPUDONE as an indicator that all memory accesses issued by the processor result from operations performed by a debugger.

Figure 10.2 shows the Cortex-R7 MPCore processor connections specific to debug request and restart and the CoreSight inputs and outputs.

Figure 10.2. Debug request restart-specific connections

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COMMRX and COMMTX

The COMMRX and COMMTX output signals enable interrupt-driven communications over the DTR. By connecting these signals to an interrupt controller, software using the debug communications channel can be interrupted whenever there is new data on the channel or when the channel is clear for transmission:

  • COMMRX is asserted when the CP14 DTR has data for the processor to read, and is deasserted when the processor reads the data. Its value is equal to the DBGDSCR[30] DTRRX full flag.

  • COMMTX is asserted when the CP14 DTR is ready for write data, and is deasserted when the processor writes the data. Its value is equal to the inverse of the DBGDSCR[29] DTRTX full flag.

DBGROMADDR and DBGSELFADDR

Cortex-R7 processors have a memory-mapped debug interface, and can access the debug and PMU registers by executing load and store instructions going through the AXI3 bus:

  • DBGROMADDR gives the base address for the ROM table that locates the physical addresses of the debug components.

  • DBGSELFADDR gives the offset from the ROM table to the physical addresses of the registers in the processor itself.

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