10.2.2. Performance monitoring events

The Cortex-R7 MPCore processor implements the architectural events described in the ARM Architecture Reference Manual. For events and the corresponding PMUEVENT signals, see Performance monitoring signals.

The PMU provides an additional set of Cortex-R7 specific events.

The ETM accepts 64 events:

The ETM can export two signals that are connected to the processor PMU. These signals are ETMEXTOUT[1] and ETMEXTOUT[2] events, and are described in Table 10.7. See the ARM® CoreSight™ ETM-R7 Technical Reference Manual for more information about the EXTOUT signals from the ETM.

Table 10.7 shows the Cortex-R7 MPCore processor events, with their associated event number, and position in the PMUEVENT bus.

Table 10.7. Cortex-R7 MPCore processor events

EventDescriptionPosition in PMUEVENT bus
Common events 
0x00Software increment[0]
0x01Instruction cache miss[1]
0x03Data cache miss[2]
0x04Data cache access[3]
0x06Data read[4]
0x07Data write[5]
0x08Instruction architecturally executed[11:6]
0x09Exception taken[12]
0x0AException returns[13]
0x0BWrite context ID[14]
0x0CSoftware change of PC[15]
0x0DImmediate branch[16]
0x0EProcedure return, other than exception return[17]
0x10Branch mispredicted or not predicted[19]
0x11Cycle countNot applicable
0x12Predictable branches[20]
0x14Instruction cache access[21]
ETM events 
0x40ETMEXTOUT[1]Not applicable
0x41ETMEXTOUT[2]Not applicable
Determinism events
0x50Number of cycles IRQs are interrupted[22]
0x51Number of cycles FIQs are interrupted[23]
ECC events
0x60Detected ECC errors on any RAMNot exported
0x61Parity error on PRED[24]
0x62Parity error on BTAC[25]
0x63Detected ECC errors on ITCM[26]
0x64Detected ECC errors on DTCM[27]
0x65Detected ECC errors on instruction cache[28]
0x66Detected ECC errors on data cache[29]
0x67Correctable ECC errors on any busNot exported
0x68Correctable ECC errors on slave bus, data write channel[30]
0x69Correctable ECC errors on peripheral master bus, data read channel[31]
0x6ACorrectable ECC errors on master 0 bus, data read channel[32]
0x6BCorrectable ECC errors on master 1 bus, data read channel[33]
0x6CDetected ECC errors on SCU RAM[34]
Software events
0x80STREX passed[35]
0x81STREX failed[36]
0x82Literal pool in TCM region[37]
Microarchitecture events
0x90DMB stall[38]
0x91ITCM access[39]
0x92DTCM access[40]
0x93Data eviction[41]
0x94SCU coherency operation (CCB request)[42]
0x95Instruction cache dependent stall[43]

Data cache dependent stall[b]


Non-cacheable no peripheral dependent stall[c]


Non-cacheable peripheral dependent stall[d]


Data cache high priority dependent stall[e]

-Reserved, tied LOW[55:48]

[a] This counter is mostly used when QoS is enabled. The core issue stage is stalled and it contains at least one instruction that it cannot dispatch.

[b] The counter counts stalls on AXI M0 with low-priority Cacheable traffic.

[c] The counter counts stalls on AXI M0 or M1 with low-priority NC/SO/Dev.

[d] The counts stall on AXI MP with high-priority SO/DEV.

[e] The counts stall on AXI M1 with high-priority when a local SRAM is in use.


You can choose whether these events are enabled or not, and exported or not, using the PMCR Register. See the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition. For a fault-tolerant system, ECC events must be exported for more visibility. To achieve this, there are some specific ECC notification signals. See Chapter 7 Fault Detection for more information.

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