10.2. Performance Monitoring Unit

The Cortex-R7 MPCore processor PMU provides eight counters to gather statistics on the operation of the processor and memory system. Each counter can count any of the 64 events available in each processor.

The PMU counters, and their associated control registers, are accessible from the internal CP15 interface and from the Debug APB interface. Table 10.1 shows the mappings of the PMU registers.

Table 10.1. Performance monitoring instructions and Debug APB mapping

Debug APB interface mappingCP15 instructionAccessResetName
0x0000, c9, c13, 2RW-PMXEVCNTR0
0x0040, c9, c13, 2RW-PMXEVCNTR1
0x0080, c9, c13, 2RW-PMXEVCNTR2
0x00C0, c9, c13, 2RW-PMXEVCNTR3
0x0100, c9, c13, 2RW-PMXEVCNTR4
0x0140, c9, c13, 2RW-PMXEVCNTR5
0x0180, c9, c13, 2RW-PMXEVCNTR6
0x01C0, c9, c13, 2RW-PMXEVCNTR7
0x07C0, c9, c13, 0 RW-PMCCNTR
0x4000, c9, c13, 1RW-PMXEVTYPER0
0x4040, c9, c13, 1RW-PMXEVTYPER1
0x4080, c9, c13, 1RW-PMXEVTYPER2
0x40C0, c9, c13, 1RW-PMXEVTYPER3
0x4100, c9, c13, 1RW-PMXEVTYPER4
0x4140, c9, c13, 1RW-PMXEVTYPER5
0x4180, c9, c13, 1RW-PMXEVTYPER6
0x41C0, c9, c13, 1RW-PMXEVTYPER7
0xC000, c9, c12, 1RW-PMCNTENSET
0xC200, c9, c12, 2RW-PMCNTENCLR
0xC400, c9, c14, 1RW-PMINTENSET
0xC600, c9, c14, 2RW-PMINTENCLR
0xC800, c9, c12, 3RW-PMOVSR
0xCA00, c9, c12, 4WO-PMSWINC
0xE040, c9, c12, 0RW0x41174000PMCR

0xE08

0, c9, c14, 0

RW[a]

0x00000000PMUSERENR
-0, c9, c12, 5RW-PMSELR

[a] Read only in user mode.


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