9.4.3. Interrupt interface register descriptions

This section shows the registers that each Cortex-R7 processor interface provides. Table 9.23 shows the Cortex-R7 MPCore processor interface registers. This section does not reproduce information about registers already described in the ARM® Generic Interrupt Controller Architecture Specification. These registers are word accessible. Any other access is unpredictable.

Table 9.23. Cortex-R7 processor interface register summary

BaseNameTypeResetWidthDescription
0x000

ICCICR

RW0x0000000032CPU Interface Control Register
0x004

ICCPMR

RW0x0000000032Interrupt Priority Mask Register[a]
0x008

ICCBPR

RW

0x3

32Binary Point Register
0x00C

ICCIAR

RO0x000003FF32Interrupt Acknowledge Register
0x010

ICCEOIR

WO-32End Of Interrupt Register
0x014

ICCRPR

RO0x000000FF32Running Priority Register
0x018

ICCHPIR

RO0x000003FF32Highest Pending Interrupt Register
0x0FC

ICCIIDR

RO0x3901243B32

CPU Interface Implementer Identification Register

[a] Only the top four bits of each 8-bit field of the register are in use.


CPU Interface Implementer Identification Register

The ICCIIDR Register characteristics are:

Purpose

Provides information about the implementer and the revision of the controller.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.23.

Figure 9.22 shows the ICCIIDR bit assignments.

Figure 9.22. ICCIIDR bit assignments

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Table 9.24 shows the ICCIIDR bit assignments

Table 9.24. ICCIIDR bit assignments

BitsValuesNameDescription
[31:20]0x390Part number

Identifies the peripheral.

[19:16]0x1Architecture version

Identifies the architecture version.

[15:12]0x0Revision number

Returns the revision number of the interrupt controller. The implementer defines the format of this field.

[11:0]0x43BImplementer

Returns the JEP106 code of the company that implemented the Cortex-R7 MPCore processor interface RTL. It uses the following construct:

[11:8]

JEP106 continuation code of the implementer.

[7]

0.

[6:0]

JEP106 code [6:0] of the implementer.


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