4.2.6. c9 registers

Table 4.7 shows the 32-bit wide CP15 system control registers when CRn is c9.

Table 4.7. c9 register summary

Op1CRmOp2NameReset Description
0c10DTCMRRUNKDTCM Region Register
1ITCMRRUNKITCM Region Register
c120PMCR0x41174000Performance Monitor Control Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1PMCNTENSET0x00000000Count Enable Set Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2PMCNTENCLR0x00000000Count Enable Clear Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
3PMOVSR0x00000000Overflow Flag Status Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
4PMSWINCUNKSoftware Increment Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
5PMSELR0x00000000Event Counter Selection Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c130PMCCNTRUNKCycle Count Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.
1PMXEVTYPERUNKEvent Selection Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2PMXEVCNTRUNKPerformance Monitor Count Registers, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c140PMUSERENR0x00000000User Enable Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1PMINTENSET0x00000000Interrupt Enable Set Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2PMINTENCLR0x00000000Interrupt Enable Clear Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

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