4.2.3. c5 registers

Table 4.4 shows the 32-bit wide CP15 system control registers when CRn is c5.

Table 4.4. c5 register summary

Op1CRmOp2NameReset Description
0c00DFSR-Data Fault Status Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1

IFSR

-Instruction Fault Status Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814