Bits[10:9] of this register are used to enable ECC checking. See Auxiliary Control Register.

These registers provide information on ECC errors. See ECC Error Registers.

The performance counters can be configured to monitor several ECC-related metrics. See Performance monitoring events for more information.

The processor contains registers that provide direct access to the caches. These registers enable the RAM analysis on error and the auto-checking of the ECC mechanisms by software. On the instruction side, these registers enable direct access to the instruction cache and to the instruction data. BTAC and PRED cannot be accessed in this way. On the data side, the tag RAM and the data cache RAM can be accessed in this way. See Cache and TCM Debug Operation Register.

Bits[15:12] of this register are used to enable ECC checking on the AXI ports. See SCU Control Register.

Bits[13:5] of these registers hold the SCU tag RAM index, and bits[1:0] show the error status. See SCU Error Bank First Entry Register and SCU Error Bank Second Entry Register.

Events related to the SCU are reported to the PMU of each processor. The performance counters can be configured to monitor several ECC-related metrics. See Performance monitoring events for more information on SCU-related events.

These registers provide information on various aspects of ECC for the SCU:

See SCU Debug tag RAM access.