7.5.1. Registers

Various processor and SCU registers are used to enable and monitor ECC:

Processor registers

The following processor registers are used in ECC:

Auxiliary Control Register (ACTLR)

Bits[10:9] of this register are used to enable ECC checking. See Auxiliary Control Register.

ECC Error Registers (DEER0-2/IEER0-2 and DTCMEER/ITCMEER)

These registers provide information on ECC errors. See ECC Error Registers.

Performance counters

The performance counters can be configured to monitor several ECC-related metrics. See Performance monitoring events for more information.

Cache and TCM Debug Operation Register (CTDOR)

The processor contains registers that provide direct access to the caches. These registers enable the RAM analysis on error and the auto-checking of the ECC mechanisms by software. On the instruction side, these registers enable direct access to the instruction cache and to the instruction data. BTAC and PRED cannot be accessed in this way. On the data side, the tag RAM and the data cache RAM can be accessed in this way. See Cache and TCM Debug Operation Register.

SCU registers

The SCU is seen as a peripheral by the processors in the Cortex-R7 MPCore processor, and has its own memory-mapped register file. The following SCU registers are used in ECC:

SCU Control Register

Bits[15:12] of this register are used to enable ECC checking on the AXI ports. See SCU Control Register.

SCU Error Bank Registers

Bits[13:5] of these registers hold the SCU tag RAM index, and bits[1:0] show the error status. See SCU Error Bank First Entry Register and SCU Error Bank Second Entry Register.

Performance counters

Events related to the SCU are reported to the PMU of each processor. The performance counters can be configured to monitor several ECC-related metrics. See Performance monitoring events for more information on SCU-related events.

SCU Debug Cache Registers

These registers provide information on various aspects of ECC for the SCU:

  • The SCU Debug Tag RAM Operation Register shows the the address and action for the SCU tag RAM access.

  • The SCU Debug Tag RAM Data Value Register and SCU Debug Tag RAM ECC Chunk Register contain the data from the memory selected by the SCU Debug Tag RAM Operation Register.

See SCU Debug tag RAM access.

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