4.2.5. c7 registers

Table 4.6 shows the 32-bit wide CP15 system control registers when CRn is c7.

Table 4.6. c7 register summary

Op1CRmOp2NameReset[a] Description
0c04NOP-No operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.
c10ICIALLUIS-Invalidate all instruction caches to PoU Inner Shareable, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
6BPIALLIS-Invalidate entire branch predictor array Inner Shareable, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c50ICIALLU-Invalidate entire instruction cache, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1ICIMVAU-Invalidate instruction cache by VA to PoU, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
4CP15ISB-Instruction Synchronization Barrier operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
6BPIALL-Invalidate entire branch predictor array, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
7BPIMVA-Invalidate MVA from branch predictors, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c61DCIMVAC-Invalidate data cache line by VA to PoC, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2DCISW-Invalidate data cache line by Set/Way, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c101DCCMVAC-Clean data cache line to PoC by VA, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2DCCSW-Clean data cache line by Set/Way. see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
4CP15DSB-Data Synchronization Barrier operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
5CP15DMB-Data Memory Barrier operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
0c111DCCMVAU-Clean data or unified cache line by VA to PoU, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c141DCCIMVAC-Clean and invalidate data cache line by VA to PoC, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2DCCISW-Clean and invalidate data cache line by Set/Way, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

[a] These registers do not have a reset value because they are write-only.


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