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There are four banks of ECC Error Registers:
One bank for the data cache.
One bank for the instruction cache.
One bank for the data TCM.
One bank for the instruction TCM.
Banks for data cache and instruction caches have three entries, DEER0-2/IEER0-2. Banks for data TCM and instruction TCM have one entry, DTCMEER/ITCMEER.
The DEER0-2/IEER0-2 and DTCMEER/ITCMEER characteristics are:
Indicate where ECC errors have occurred.
The DEER0-2/IEER0-2 and DTCMEER/ITCMEER are only accessible in privileged mode.
Available in all configurations.
See the register summary in Table 4.9.
Table 4.39 shows the DEER0-2 bit assignments.
Table 4.39. DEER0-2 bit assignments
| Bits | Function |
|---|---|
| [31:28] | Way affected in one-hot encoding. |
| [27:26] | Reserved. RAZ/WI. |
| [25] | A fatal error has occurred. |
| [24:19] | Reserved. RAZ/WI. |
| [18] | Error occurred in Data RAM. |
| [17] | Error occurred in Tag RAM. |
| [16] | Error occurred in SCU RAM. |
| [15:14] | Reserved. RAZ/WI. |
| [13:5] | Faulty address where error has occurred. |
| [4:2] | Faulty word affected by ECC error. |
| [1] | Error is hard, that is, only software can write on it. |
| [0] | This entry contains valid information. |
Table 4.40 shows the IEER0-2 bit assignments.
Table 4.40. IEER0-2 bit assignments
| Bits | Function |
|---|---|
| [31:28] | Way affected in one-hot encoding. |
| [27:26] | Reserved. RAZ/WI. |
| [25] | A fatal error has occurred. |
| [24:14] | Reserved. RAZ/WI. |
| [13:5] | Faulty address where error has occurred. |
| [4:2] | Faulty word affected by ECC error. |
| [1] | Error is hard, that is, only software can write on it. |
| [0] | This entry contains valid information. |
Table 4.41 shows the DTCMEER/ITCMEER bit assignments.
Table 4.41. DTCMEER/ITCMEER bit assignments
| Bits | Function |
|---|---|
| [31:26] | Reserved. RAZ/WI. |
| [25] | A fatal error has occurred. |
| [24:17] | Reserved. RAZ/WI. |
| [16:2] | Faulty address where error has occurred. |
| [1] | Error is hard, that is, only software can write on it. |
| [0] | This entry contains valid information. |
When an error is detected by the processor circuitry, the first available ECC Error Register is updated with the memory information of where the error has been found, for example, index, way, or memory type, and bit [0] is set to 1. Bit [1] can only be accessed by the software and is used to mark entries where there are hard errors. Writing zeros to bits [25] and [1:0] enables their contents to be reset. Resetting the ECC information is therefore possible by writing these six registers successively, two for each entry.
If bit [16] is set to 1, the error has been detected by the SCU, therefore this index-way pair is also present in the SCU error bank. When resetting an entry, if this bit is set, you must clear the corresponding SCU entry to maintain the coherence between the SCU error bank and the D-side error bank. This bit is only accessible for the Data Side.
Table 4.42 shows the meaning of the error status bits.
Table 4.42. Error status bit encoding
| Bits[1:0] | Meaning |
|---|---|
| 00 | No error. Entry available, no index masking, not yet processed by the external system. |
| 01 | Unanalyzed error. Entry not available, index masking, not yet processed by the external system. It can be either soft or hard. This state is entered when any ECC error occurs. |
| 10 | Not used. |
| 11 | Permanent error. Entry not available, index masking, already processed by the external system. |
All errors captured between two analyses of the global monitor or left in the bank by it are visible in this bank, as long as the bank has not been filled.
To access the DEER0-2, read or write the CP15 register with:
MRC p15, 0, <Rd>, c15, c2, n; Read ECC entry no. n, n in set [0, 1, 2]
MCR p15, 0, <Rd>, c15, c2, n; Write ECC entry no. n, n in set [0, 1, 2]
To access the IEER0-2, read or write the CP15 register with:
MRC p15, 0, <Rd>, c15, c3, n; Read ECC entry no. n, n in set [0, 1, 2]
MCR p15, 0, <Rd>, c15, c3, n; Write ECC entry no. n, n in set [0, 1, 2]
To access the DTCMEER, read or write the CP15 register with:
MRC p15, 0, <Rd>, c15, c4, 0; Read TCM ECC entry
MCR p15, 0, <Rd>, c15, c4, 0; Write TCM ECC entry
To access the ITCMEER, read or write the CP15 register with:
MRC p15, 0, <Rd>, c15, c5, 0; Read TCM ECC entry
MCR p15, 0, <Rd>, c15, c5, 0; Write TCM ECC entry
| Copyright © 2012, 2014 ARM. All rights reserved. | ARM DDI 0458C |
| Non-Confidential | ID112814 |
| PDF version | |
| Home > System Control > Register descriptions > ECC Error Registers |