4.2.1. c0 registers

Table 4.2 shows the 32-bit wide CP15 system control registers when CRn is c0.

Table 4.2. c0 register summary

Op1CRmOp2NameReset Description
0c00

MIDR

0x410FC171

Main ID Register

1

CTR

0x8333C003

Cache Type Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

2TCMTR

Implementation dependent[a]

TCM Type Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

4MPUIR

Implementation dependent[b]

MPU Type Register
5MPIDRImplementation dependent[c]

Multiprocessor Affinity Register

6REVIDRImplementation dependent

Revision ID Register

c10ID_PFR00x00000131Processor Feature Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1ID_PFR10x00000001Processor Feature Register 1, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2ID_DFR00x00010404Debug Feature Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.
3ID_AFR00x00000000Auxiliary Feature Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
4ID_MMFR00x00110130Memory Model Feature Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
5ID_MMFR10x00000000Memory Model Feature Register 1, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
6ID_MMFR20x01200000Memory Model Feature Register 2, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
7ID_MMFR30x00002111Memory Model Feature Register 3, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
c20ID_ISAR00x02101111Instruction Set Attributes Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1ID_ISAR10x13112111Instruction Set Attributes Register 1, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
2ID_ISAR20x21232141Instruction Set Attributes Register 2, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
3ID_ISAR30x01112131Instruction Set Attributes Register 3, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
4ID_ISAR40x00010142Instruction Set Attributes Register 4, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
1c00CCSIDRUNKCache Size ID Register
1CLIDR

Implementation dependent[d]

Cache Level ID Register
7

AIDR

0x00000000Auxiliary ID Register
2c00CSSELR

Implementation dependent

Cache Size Selection Register

[a] If TCMs are implemented 0x80010001.

If TCMs are not implemented 0x00000000.

[b] For 12 MPU regions 0x00000c00.

For 16 MPU regions 0x00001000.

[c] Dependent on external signal CLUSTERID and the number of configured processors in the Cortex-R7 MPCore processor.

[d] If cache present 0x09200003.

If cache not present 0x00000000.


Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814