8.2.2. Memory types

The ARM Architecture defines a set of memory types with characteristics that are suited to particular devices. There are three mutually exclusive memory type attributes:

MPU memory regions must each be assigned a memory type attribute. Table 8.1 shows a summary of the memory types.

Table 8.1. Memory attributes summary

Memory type attributeShareable or Non-shareableOther attributesDescription
Strongly Ordered--All memory accesses to Strongly Ordered memory occur in program order. All Strongly Ordered accesses are assumed to be shareable.
DeviceShareable-For memory-mapped peripherals that two processors share.
 Non-shareable-For memory-mapped peripherals that only a single processor uses.
NormalShareableNon-cacheable Write-back CacheableFor normal memory that is shareable between two processors.
 Non-shareableNon-cacheable Write-back CacheableFor normal memory that only a single processor uses.

For more information on memory attributes and types, memory barriers, and ordering requirements for memory accesses, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

Using memory types

The memory system contains a store buffer.This helps to improve the throughput of accesses to Normal type memory. Because of the ordering rules that they must follow, accesses to other types of memory typically have a lower throughput and higher latency than accesses to Normal memory. In particular, reads from Device or Strongly Ordered memory must first drain the store buffer of all writes to Device or Strongly Ordered memory:

Similarly, when it is accessing Strongly Ordered or Device type memory, the processor's response to interrupts is modified, and the interrupt response latency is longer.

To ensure optimum performance, you must understand the architectural semantics of the different memory types. Use Device memory type for appropriate memory regions, typically peripherals, and only use Strongly Ordered memory type for memory regions where it is essential.

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