11.1.1. Supported AXI3 transfers

The Cortex-R7 MPCore processor master ports can generate all possible AXI3 transactions from ACP traffic.

Transactions from the individual processors use only the following subset of possible AXI3 transactions:

The following points apply to AXI3 transactions:

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814