10.2.1. PMU management registers

The PMU management registers define the standardized set of registers that is implemented by all CoreSight components.

Table 10.2 shows the contents of the PMU management registers for the Cortex-R7 MPCore debug unit.

Table 10.2. PMU management registers

OffsetRegister numberAccessMnemonicDescription
0xD00-0xDFC832-895RO-Processor ID Registers.
0xF04-0xF9C961-999RAZ-Reserved for Management Register expansion.
0xFC81010RODEVIDDevice Identifier.
0xFD0-0xFFC1012-1023R-CoreSight Identification Registers.

Processor ID Registers

The Processor ID Registers are read-only registers that return the same values as the corresponding CP15 ID Code Register and Feature ID Register.

Table 10.3 shows the offset value, register number, mnemonic, and description that are associated with each Processor ID Register.

Table 10.3. Processor Identifier Registers

Offset (hex)Register numberMnemonicAccessRegister value Description
0xD00832CPUIDRO0x80000n0m[a]ID Code Register
0xD04833CTRRO0x8333C003Cache Type Register

0x80010001[b] 0x00000000 [c]

TCM Type Register
0xD20840ID_PFR0RO0x00000131Processor Feature Register 0
0xD24841ID_PFR1RO0x00000001Processor Feature Register 1
0xD28842ID_DFR0RO0x00010404Debug Feature Register 0
0xD2C843ID_AFR0RAZ-Auxiliary Feature Register 0
0xD30844ID_MMFR0RO0x00110130Memory Model Feature Register 0
0xD34845ID_MMFR1RO0x00000000Memory Model Feature Register 1
0xD38846ID_MMFR2RO0x01200000Memory Model Feature Register 2
0xD3C847ID_MMFR3RO0x00002111Memory Model Feature Register 3
0xD40848ID_ISAR0RO0x02101111Instruction Set Attribute Register 0
0xD44849ID_ISAR1RO0x13112111Instruction Set Attribute Register 1
0xD48850ID_ISAR2RO0x21232141Instruction Set Attribute Register 2
0xD4C851ID_ISAR3RO0x01112131Instruction Set Attribute Register 3
0xD50852ID_ISAR4RO0x00010142Instruction Set Attribute Register 4
0xD54853ID_ISAR5RAZ-Instruction Set Attribute Register 5

[a] n = CLUSTERID input m = processor number (0x0 for processor 0, 0x1 for processor 1).

[b] If TCMs are present.

[c] If TCMs are not present.

CoreSight Identification Registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight components. Only bits[7:0] of each register are used.

The Component Identification Registers identify the processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

Table 10.4 shows the offset value, register number, value, and description that are associated with each Peripheral Identification Register.

Table 10.4. Peripheral Identification Registers

Offset (hex)Register numberValueDescription
0xFD010120x04Peripheral Identification Register 4
0xFE010160xB7Peripheral Identification Register 0
0xFE410170xB9Peripheral Identification Register 1
0xFE810180xrB[a]Peripheral Identification Register 2
0xFEC10190x00Peripheral Identification Register 3

[a] r represents the variant. For r0p0, this is 0.

Table 10.5 shows the offset value, register number, and value that are associated with each Component Identification Register.

Table 10.5. Component Identification Registers

Offset (hex)Register numberValueDescription
0xFF010200x0DComponent Identification Register 0
0xFF410210x90Component Identification Register 1
0xFF810220x05Component Identification Register 2
0xFFC10230xB1Component Identification Register 3

PMU APB interface

Table 10.6 shows the PMU register names and corresponding addresses on the APB interface.

Table 10.6. PMU register names and APB addresses

PMU register nameDebug APB address
PMU event counter 0 0x000
PMU event counter 1 0x004
PMU event counter 2 0x008
PMU event counter 3 0x00C
PMU event counter 4 0x010
PMU event counter 50x014
PMU event counter 60x018
PMU event counter 70x01C
PMU cycle counter0x07C
PMU event type 0 0x400
PMU event type 1 0x404
PMU event type 2 0x408
PMU event type 3 0x40C
PMU event type 4 0x410
PMU event type 50x414
PMU event type 60x418
PMU event type 70x41C
PMU count enable set0xC00
PMU count enable clear0xC20
PMU interrupt enable set0xC40
PMU interrupt enable clear0xC60
PMU overflow flag status0xC80
PMU software increment0xCA0
PMU control0xE04
PMU user enable0xE08

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