4.3.12. MPU memory region programming registers

The MPU memory region programming registers program the MPU regions.

There is one register that specifies which set of region registers is to be accessed. See MPU Memory Region Number Registers. Each region has its own register to specify:

You can implement the processor with 12 or 16 regions.

Note

  • When the MPU is enabled:

    • The MPU determines the access permissions for all accesses to memory, including the TCMs. Therefore, you must ensure that the memory regions in the MPU are programmed to cover the complete TCM address space with the appropriate access permissions. You must define at least one of the regions in the MPU.

    • An access to an undefined area of memory generates a background fault.

  • For the TCM space, the processor uses the access permissions but ignores the region attributes from MPU.

    CP15, c9 sets the location of the TCM base address. For more information see DTCM Region Register and ITCM Region Register.

MPU Region Base Address Registers

The DRBAR characteristics are:

Purpose

Describe the base address of the region specified by the RGNR. The region base address must always align to the region size.

Usage constraints

The DRBAR are only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.5.

Figure 4.11 shows the DRBAR bit assignments.

Figure 4.11. DRBAR bit assignments

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Table 4.28 shows the DRBAR bit assignments.

Table 4.28. DRBAR bit assignments

Bits

NameFunction
[31:5] Base addressPhysical base address. Defines the base address of a region.
[4:0]ReservedSBZ

To access the DRBAR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c1, 0 ; Read MPU Region Base Address Register
MCR p15, 0, <Rd>, c6, c1, 0 ; Write MPU Region Base Address Register

MPU Region Size and Enable Registers

The DRSR characteristics are:

Purpose
  • Specify the size of the region specified by the RGNR.

  • Identify the address ranges that are used for a particular region.

  • Enable or disable the region, and its sub-regions, specified by the RGNR.

Usage constraints

The DRSR are only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.5.

Figure 4.12 shows the DRSR bit assignments.

Figure 4.12. DRSR bit assignments

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Table 4.29 shows the DRSR bit assignments.

Table 4.29. DRSR bit assignments

Bits NameFunction
[31:16] ReservedSBZ.
[15:8]Sub-region disable

Each bit position represents a sub-region, 0-7[a].

Bit[8] corresponds to sub-region 0

...

Bit[15] corresponds to sub-region 7.

The meaning of each bit is:

0

Address range is part of this region.

1

Address range is not part of this region.

[7:6]ReservedSBZ.
[5:1]Region size

Defines the region size:

0b00000-0b00110

unpredictable.

0b00111

256 bytes.

0b01000

512 bytes.

0b01001

1KB.

0b01010

2KB.

0b01011

4KB.

0b01100

8KB.

0b01101

16KB.

0b01110

32KB.

0b01111

64KB.

0b10000

128KB.

0b10001

256KB.

0b10010

512KB.

0b10011

1MB.

0b10100

2MB.

0b10101

4MB.

0b10110

8MB.

0b10111

16MB.

0b11000

32MB.

0b11001

64MB.

0b11010

128MB.

0b11011

256MB.

0b11100

512MB.

0b11101

1GB.

0b11110

2GB.

0b11111

4GB.

[0]

Enable

Enables or disables a memory region:

0

Memory region disabled. Memory regions are disabled on reset.

1

Memory region enabled. A memory region must be enabled before it is used.

[a] Sub-region 0 covers the least significant addresses in the region, while sub-region 7 covers the most significant addresses in the region. For more information, see Subregions.


To access the DRSR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c1, 2 ; Read Data MPU Region Size and Enable Register
MCR p15, 0, <Rd>, c6, c1, 2 ; Write Data MPU Region Size and Enable Register

Writing a region size that is outside the range results in unpredictable behavior.

MPU Region Access Control Registers

The DRACR characteristics are:

Purpose

Hold the region attributes and access permissions for the region specified by the RGNR.

Usage constraints

The DRACR are only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.5.

Figure 4.13 shows the DRACR bit assignments.

Figure 4.13. DRACR bit assignments

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Table 4.30 shows the DRACR bit assignments.

Table 4.30. DRACR bit assignments

Bits

NameFunction

[31:13]

ReservedSBZ.
[12]XN

Execute never. Determines if a region of memory is executable:

0

All instruction fetches enabled.

1

No instruction fetches enabled.

[11]ReservedSBZ
[10:8]APAccess permission. Defines the data access permissions. For more information on AP bit values, see Table 4.31.
[7:6]ReservedSBZ.
[5:3]TEXType extension. Defines the type extension attribute[a].
[2]S

Share. Determines if the memory region is Shareable or Non-shareable:

0

Non-shareable.

1

Shareable.

This bit only applies to Normal, not Device or Strongly Ordered memory.

[1]C

C bit[a]:

[0]B

B bit[a]:

[a] For more information on this region attribute, see Table 8.2.


Table 4.31 shows the AP bit values that determine the permissions for privileged and user data access.

Table 4.31. Access data permission bit encoding

AP bit valuesPrivileged permissionsUser permissionsDescription
0b000No accessNo access

All accesses generate a permission fault

0b001Read/writeNo access

Privileged access only

0b010Read/writeRead-only

Writes in user mode generate permission faults

0b011Read/writeRead/write

Full access

0b100UNPUNP

Reserved

0b101Read-onlyNo access

Privileged read-only

0b110Read-onlyRead-only

Privileged/user read-only

0b111UNPUNP

Reserved


To access the DRACR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c1, 4 ; Read Region Access Control Register
MCR p15, 0, <Rd>, c6, c1, 4 ; Write Region Access Control Register

To execute instructions in user and privileged modes:

  • The region must have read access as defined by the AP bits.

  • The XN bit must be set to 0.

MPU Memory Region Number Registers

The RGNR characteristics are:

Purpose

Determines which register is accessed. There is one register for each implemented memory region.

Usage constraints

The RGNR are only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.5.

Figure 4.14 shows the RGNR bit assignments.

Figure 4.14. RGNR bit assignments

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Table 4.32 shows the RGNR bit assignments.

Table 4.32. RGNR bit assignments

Bits

NameFunction
[31:4]ReservedSBZ.
[3:0]RegionDefines the group of registers to be accessed. Read the MPU Type Register to determine the number of supported regions, see MPU Type Register.

To access the RGNR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c2, 0 ; Read MPU Memory Region Number Register
MCR p15, 0, <Rd>, c6, c2, 0 ; Write MPU Memory Region Number Register

Writing this register with a value greater than or equal to the number of regions from the MPU Type Register is unpredictable. Associated register bank accesses are also unpredictable.

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