1.1. About the Cortex-R7 MPCore processor

The Cortex-R7 MPCore processor is a mid-range processor for use in deeply-embedded, real-time systems, and consists of one or two Cortex-R7 processors in a single MPCore device. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.

The pipeline has a dual Arithmetic Logic Unit (ALU), with dual-issuing of instructions for efficient utilization of other resources such as the register file. The processor has Level 1 (L1) data cache coherency in a cluster with up to two processors, and an optional hardware Accelerator Coherency Port (ACP) is provided to reduce software cache maintenance operations when sharing memory regions with other masters.

Interrupt latency is kept low by interrupting and restarting load-store multiple instructions, and by use of an integrated interrupt controller. The Cortex-R7 MPCore processor provides two specialized memory solutions for low-latency and determinism:

Optional Error Correcting Code (ECC) is used on the processor ports and in L1 memories to provide improved reliability and address fault-critical applications.

Many of the features, including the caches, TCM, and ECC are configurable so that a given processor implementation can be tailored to the application for efficient power and area usage.

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