2.5.7. Private memory region

All registers accessible by all processors within a Cortex-R7 MPCore design are grouped into two contiguous 4KB pages accessed through a dedicated internal bus. The base address of these pages is defined by the PERIPHBASE[31:13] inputs. See Configuration signals for more information on PERIPHBASE[31:13].

Global control registers and peripherals must be accessed through memory-mapped transfers to the private memory region.

Memory regions used for these registers must be marked as Device or Strongly-ordered in the MPU.

Access to the private memory region is little-endian only.

Access these registers with single load/store instructions. Load or store multiple accesses cause an abort to the requesting processor and the Fault Status Register shows this as a SLVERR.

Table 2.8 shows the permitted access sizes for the private memory regions.

Table 2.8. Permitted access sizes for private memory regions

Private memory regionPermitted access sizes
ByteHalfword[a]Word[b]Doubleword[a]
Global timer, private timers, and watchdogs NoNoYesNo
SCU registersYesNoYesNo
Processor interrupt interfaces
Interrupt distributor

[a] Halfword or doubleword accesses cause an abort to the requesting processor and the Fault Status Register shows this as a SLVERR.

[b] A word access with strobes not all set causes an abort to the requesting processor and the Fault Status Register shows this as a SLVERR.


The ACP cannot access any of the registers in this memory region.

Table 2.9 shows register addresses for the Cortex-R7 MPCore processor relative to this base address.

Table 2.9. Cortex-R7 MPCore private memory region

Offset from PERIPHBASE[31:13]

PeripheralDescription
0x0000-0x00FCSCU registersSCU registers.
0x0100-0x01FFInterrupt controller interfaces Interrupt controller.
0x0200-0x02FFGlobal timerGlobal timer.
0x0300-0x03FFReservedAny access to this region causes a SLVERR abort exception.
0x0400-0x04FF
0x0500-0x05FF
0x0600-0x06FFPrivate timers and watchdogs Private timer and watchdog.
0x0700-0x07FFReserved

Any access to this region causes a SLVERR abort exception.

0x0800-0x08FF
0x0900-0x09FF
0x0A00-0x0AFF
0x0B00-0x0FFF
0x1000-0x1FFFInterrupt DistributorDistributor register descriptions.

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