11.2.1. Early BRESP

According to the AXI3 specification, BRESP answers on response channels must be returned to the master only when the last data has been sent by the master. Cortex-R7 MPCore processors can also deal with BRESP answers returned as soon as address has been accepted by the slave, regardless of whether data is sent or not. This enables the processor to provide a higher bandwidth for writes if the slave can support the Early BRESP feature. Cortex-R7 MPCore processors set the AWUSER[8] bit to indicate to the slave that it can accept an early BRESP answer for this access. This feature can optimize the performance of the processor, but the Early BRESP feature generates non-AXI3 compliant requests. When a slave receives a write request with AWUSER[8] set, it can either give the BRESP answer after the last data is received, AXI3 compliant, or in advance, non-AXI3 compliant. The L2C-310 Cache Controller supports this non-AXI3 compliant feature.

This feature is enabled by default. The Cortex-R7 MPCore processor does not require any programming to enable this feature.


To support this optimization, you must program the L2C-310 Cache Controller. See the CoreLink Level 2 Cache Controller (L2C-310) Technical Reference Manual .

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