11.2. Optimized accesses to the L2 memory interface

This section describes optimized accesses to the L2 memory interface. These optimized accesses can generate non-AXI3 compliant requests on the AXI master ports. These non-AXI compliant requests must be generated only when the slaves connected on the AXI master ports can support them. The L2C-310 Cache Controller supports these types of requests. The following subsections describe the requests:

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C