11.6.1. ACP requests

The read and write requests performed on the ACP behave differently depending on whether the request is coherent or not. ACP requests behavior is as follows:

ACP coherent read requests

An ACP read request is coherent when ARUSER[0] = 1 and ARCACHE[1] = 1, and ARVALID is asserted.

In this case, the SCU enforces coherency.

When the data is present in one of the processors in the Cortex-R7 MPCore design, the data is read directly from the relevant processor, and returned to the ACP port.

When the data is not present in any of the processors, the read request is issued on one of the AXI3 master ports, along with all its AXI parameters, with the exception of the locked attribute.

ACP non-coherent read requests

An ACP read request is non-coherent when ARUSER[0] = 0 or ARCACHE[1] = 0, and ARVALID is asserted.

In this case, the SCU does not enforces coherency, and the read request is directly forwarded to one of the available AXI3 master ports.

ACP coherent write requests

An ACP write request is coherent when AWUSER[0] = 1 and AWCACHE[1] =1, and AWVALID is asserted.

In this case, the SCU enforces coherency.

When the data is present in one of the processors in the Cortex-R7 MPCore design, the data is first cleaned and invalidated from the relevant processor.

When the data is not present in any of the processors, or when it has been cleaned and invalidated, the write request is issued on one of the AXI3 master ports, along with all corresponding AXI3 parameters except for the locked attribute.

ACP non-coherent write requests

An ACP write request is non-coherent when AWUSER[0] = 1 or AWCACHE[1] = 0, and AWVALID is asserted.

In this case, the SCU does not enforce coherency, and the write request is forwarded directly to one of the available AXI3 master ports.

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