2.4.1. Individual processor power management

Placeholders for clamps are inserted around each processor to simplify implementation of different power domains. See the ARM® Cortex®-R7 MPCore Configuration and Sign-off Guide for implementation information about the different power domains and the signals that require specific clamp values. Software is responsible for signaling to the Snoop Control Unit and the interrupt controller that a processor is shut off so that the processor can be seen as non-existent in the cluster. Table 2.2 shows the power modes and the wake-up mechanisms for each mode:

Table 2.2. Processor power modes

ModeDescriptionWake-up mechanism
RunEverything is clocked and powered-up.-
StandbyThe processor clock is stopped. Only logic required for wake-up is still active.Standard standby mode wake up events.
Standby mode with RAM retentionThe processor clock is stopped. Only logic required for wake-up is still active. RAMs are in retention.
Dynamic RAM retentionSome RAM arrays are put in retention dynamically, that is, if they are not used or are temporarily disabled.Normal request from processor logic.
DormantEverything is powered off except RAM arrays that are in retention mode.External wake-up event to the power controller, that can perform a reset of the processor.
ShutdownEverything is powered-off.

Entry to Dormant or powered-off mode must be controlled through an external power controller. The CPU Power Status Register in the SCU is used in conjunction with CPU WFI entry flag to signal to the power controller the power domain that it can cut, using the PWRCTL bus. See SCU CPU Power Status Register.

Entry to or exit from Standby mode with RAM retention or dynamic RAM retention must controlled through an external power controller. See the ARM® Cortex®-R7 MPCore Configuration and Sign-off Guide for more information on the interface for RAM retention.

The following sections describe the processor power modes and the power management controller:

Run mode

Run mode is the normal mode of operation, where all of the functionality of the processor is available. Everything is clocked and powered-up.

Standby modes

There are two standby modes in Cortex-R7 processors:

Wait for Interrupt

Wait for Interrupt (WFI) is a feature of the ARMv7-R architecture that puts the processor in idle mode by disabling most of the clocks in the processor while keeping the processor powered up. Only the logic required for wake-up is still active. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFI mode. A processor enters WFI mode by executing the WFI instruction.

When executing the WFI instruction, the processor waits for all instructions in the processor to complete before entering the idle mode.

While the processor is in WFI mode, the clocks in the processor are temporarily enabled without causing the processor to exit WFI mode, when any of the following events are detected:

  • A snoop request that must be serviced by the processor L1 data cache.

  • An APB access to the debug or trace registers residing in the processor power domain.

  • An AXI TCM slave port access can also temporarily enable the processor without causing the processor to exit WFI mode.

Exit from WFI mode occurs when the processor detects a reset or one of the WFI wake up events as described in the ARM Architecture Reference Manual. CP15 broadcasting operations also force an exit from WFI mode.

On entry into WFI mode, STANDBYWFI for that processor is asserted. Assertion of STANDBYWFI guarantees that the processor is in idle mode.

Note

If the ETM is present, the ETMACTIVE0/1 primary output must be taken into account to ensure the ETM has completed tracing.

STANDBYWFI continues to assert even if the clocks in the processor are temporarily enabled because of:

  • A L1 Cache Controller snoop request, if present.

  • An APB access.

  • An AXI TCM slave port request.

Wait for Event

Wait for Event (WFE) is a feature of the ARMv7-R architecture that uses a locking mechanism based on events to put the processor in idle mode by disabling most of the clocks in the processor while keeping the processor powered up. This reduces the power drawn to the static leakage current, leaving a small clock power overhead to enable the processor to wake up from WFE mode.

A processor enters WFE mode by executing the WFE instruction. When executing the WFE instruction, the processor waits for all instructions in the processor to complete before entering the idle mode. The WFE instruction ensures that all explicit memory accesses, that are prior to the WFE instruction in program order, have completed.

While the processor is in WFE mode, the clocks in the processor are temporarily enabled without causing the processor to exit out of WFE mode, when any of the following events are detected:

  • A snoop request that must be serviced by the processor L1 data cache.

  • An APB access to the debug or trace registers residing in the processor power domain.

  • An AXI TCM slave port access can also temporarily enable the processor without causing the processor to exit WFI mode.

Exit from WFE mode occurs when the processor detects a reset, an AXI TCM slave port request, the assertion of the EVENTI input signal, or one of the WFE wake up events as described in the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition. CP15 broadcasting operations also force an exit from WFE mode.

On entry into WFE mode, STANDBYWFE for that processor is asserted. Assertion of STANDBYWFE guarantees that the processor is in idle mode. STANDBYWFE continues to assert even if the clocks in the processor are temporarily enabled because of:

  • An L1 Cache Controller snoop request, if present.

  • An APB access.

  • An AXI TCM slave port request.

Standby mode with RAM retention

The processor logic is in WFI mode, and the RAM arrays are in retention mode. The RAM can be:

  • The entire instruction cache.

  • The entire data cache.

  • The entire ITCM.

  • The entire DTCM.

  • The Prediction RAMs, BTAC and PRED.

  • The SCU Tag RAM, if both processors are in WFI.

A WFI instruction must be executed. The STANDBYWFI primary output indicates the WFI mode. A temporary wake-up of the RAM can happen:

  • On L1 data cache when a snoop coherency request occurs.

  • On DTCM when an AXI TCM slave port request to the data TCM occurs.

  • On ITCM when an AXI TCM slave port request to the instruction TCM occurs.

To avoid waking up the data cache when the processor is in WFI, you can exclude the individual processor from the coherency domain. To do this, the state of the processor must be saved in the same way as when entering Dormant mode. The processor then indicates to the power controller that the device is ready to be powered down in the same way as when entering Dormant mode. The external power controller can then put the RAM in retention.

For information about the entry and exit signals, and the protocol to handle RAM retention, see the ARM® Cortex®-R7 MPCore Configuration and Sign-off Guide.

Dynamic RAM retention

Some RAM arrays are put in retention dynamically, that is, if they are not used or are temporarily disabled. The RAM can be:

  • The entire instruction cache or data cache.

  • The entire ITCM or DTCM.

  • A subset of the TCMs, using a number of address bits to select the address range of the TCMs.

Note

The Prediction RAMs, that is, BTAC and PRED, and the SCU Tag RAM are not affected in this mode.

The external power controller determines when to put the RAMs in retention, and when to wake them up.For information about the entry and exit signals, and the protocol to handle RAM retention, see the ARM® Cortex®-R7 MPCore Configuration and Sign-off Guide.

Dormant mode

Dormant mode is designed to enable an individual processor to be powered down, while leaving the RAMs powered up and maintaining their state.

The RAM blocks that are to remain powered up must be implemented on a separate power domain, and there is a requirement to clamp all of the inputs to the RAMs to a known logic level, with the chip enable being held inactive. This clamping is not implemented in gates as part of the default synthesis flow because it would contribute to a tight critical path. Implementations that want to implement Dormant mode must add these clamps around the RAMs, either as explicit gates in the RAM power domain, or as pull-down transistors that clamp the values while the processor is powered down. All RAM blocks must remain powered up during Dormant mode.

Before entering Dormant mode, the state of the processor, excluding the contents of the RAMs that remain powered up in dormant mode, must be saved to external memory. These state saving operations must ensure that the following occur:

  • All ARM registers, including CPSR and SPSR registers are saved.

  • All system registers are saved.

  • All debug-related state must be saved.

  • The processor must correctly set the CPU Power Status Register in the SCU so that it enters Dormant Mode. See SCU CPU Power Status Register.

  • A Data Synchronization Barrier instruction is executed to ensure that all state saving has been completed.

  • The processor then communicates with the power controller that it is ready to enter dormant mode by performing a WFI instruction so that power control output reflects the value of SCU CPU Power Status Register. See SCU CPU Power Status Register.

Note

If the ETM is present, the ETMACTIVE0/1 primary output must be taken into account to ensure that the ETM has completed tracing before powering-off the processor or the ETM.

Transition from Dormant mode to Run mode is triggered by the external power controller. The external power controller must assert reset to the processor until the power is restored. After power is restored, the processor leaves reset and, by interrogating the power control register in the SCU, can determine that the saved state must be restored.

Figure 2.3 shows the powerdown and powerup sequence.

Figure 2.3. Powerup and powerdown sequence

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Shutdown mode

Shutdown mode has the entire device powered down, and all state, including cache, must be saved externally by software. The part is returned to the run state by the assertion of reset. This state saving is performed with interrupts disabled, and finishes with a DSB operation. The processor then indicates to the power controller that the device is ready to be powered down in the same way as when entering Dormant mode but, in this case, the processor must set the power mode in the SCU CPU Power Status Register to powerdown.

Note

If the ETM is present, the ETMACTIVE0/1 primary output must be taken into account to ensure that the ETM has completed tracing before powering-off the processor or the ETM.

Communication to the power management controller

Communication between the processor and the external power management controller can be performed using the PWRCTLOn Cortex-R7 MPCore output signals and Cortex-R7 MPCore input clamp signals.

The PWRCTLOn Cortex-R7 MPCore output signals constrain the external power management controller. The value of PWRCTLOn depends on the value of the SCU CPU Power Status Register. See SCU CPU Power Status Register. The SCU CPU Power Status Register value is only copied to PWRCTLOn after the individual processor signals that it is ready to enter low power mode by executing a WFI instruction and subsequent STANDBYWFI output assertion.

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