1.5. Configurable options

Table 1.1 shows the features of the Cortex-R7 MPCore processor that can be configured using either build or pin configurations. See Product documentation and design flow for information about configuration of the processor. Many of these features, if included, can also be enabled and disabled during software configuration.

Table 1.1. Configurable options

FeatureRange of optionsSub-optionsBuild or pin configuration
Number of processors and optional redundancySingle processor, no redundancyOne processorBuild
Single processor, with redundancyOne processor built as lock-stepBuild
Dual processor, no redundancyTwo processorsBuild
Dual processor, redundant processorTwo processors built as split/lock, lock-step modeBuild and lock-step mode pin = 1
Two processors built as split/lock, normal modeBuild and lock-step mode pin = 0
Instruction cache No instruction cache[a]-Build
Instruction cache included

No ECC[b]

64-bit ECC

Build

4KB, 8KB, 16KB, 32KB, or 64KB

Build
Data cache No data cache[c]-Build
Data cache included

No ECC[b]

32-bit ECC

Build

4KB, 8KB, 16KB, 32KB, or 64KB

Build
Instruction TCM No Instruction TCM-Build
Instruction TCM included

No ECC[b]

64-bit ECC

Build

4KB, 8KB, 16KB, 32KB, 64KB, or 128KB

Build
Data TCM No Data TCM-Build
Data TCM included

No ECC[b]

32-bit ECC

Build

4KB, 8KB, 16KB, 32KB, 64KB, or 128KB

Build
Branch Target Address Cache (BTAC) size256, 512, 1024, 2048, or 4096 entries, default is 512-[b]Build
PREDictor (PRED) RAM size1024, 2048, or 4096 entries, default is 4096-[b]Build
FPUNot included-Build
FPU includedSingle-precision implementationBuild
Double-precision implementationBuild
MPUNumber of regions12 region optionBuild
16 region optionBuild
AXI master ports1 or 21Build
2, with address filteringBuild and pin
ETM Included or not-Build
Memory Reconstruction Port (MRP)Included or not-Build
Support for ECCUsed or not-Build
Number of interrupts0-480 in range of 32-Build

[a] If you select no instruction cache, you must also select no data cache.

[b] The ECC parameter is global for the instruction and data cache RAMs, and ITCM and DTCM.

BTAC and PRED RAM are protected by parity, initiated using the same ECC parameter.

[c] If you select no data cache, you must also select no instruction cache.


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