11.2.2. SCU speculative coherent requests

This optimization is available for Cortex-R7 MPCore processors only, and only if the L2C-310 Cache Controller is present in the design.

When this feature is enabled, coherent linefill requests are sent speculatively to the L2C-310 Cache Controller in parallel with the SCU tag look-up. If the tag look-up misses, the confirmed linefill is sent to the L2C-310 and gets RDATA earlier because the data request was already initiated by the speculative request. When filtering is enabled, only port 0 can receive speculative linefills.

To support this optimization in the Cortex-R7 MPCore processor:

  1. Program the L2C-310 Cache Controller. See the CoreLink Level 2 Cache Controller (L2C-310) Technical Reference Manual.

  2. Set bit[3] of the SCU Control Register. See SCU Control Register.


You cannot use this feature when bus ECC is implemented and the L2C-310 Cache Controller is connected.

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