11.1.2. AXI3 USER bits

The following sections describe the AXI3 USER bits encodings:

Read address channel of AXI master 0, ARUSERM0[8:0]

Table 11.2 shows the bit encodings for ARUSERM0[8:0]

Table 11.2. ARUSERM0[8:0] encodings

BitsNameDescription
[8:7]Transaction type
0b00

Processor 0 transaction.

00b10

Processor 1 transaction.

0b01

ACP transaction.

00b11

Reserved.

[6]Speculative linefill hintSpeculative linefill, used with L2C-310 Cache Controller.
[5]Reserved0b0
[4:1]Inner attributes
0b0000

Strongly Ordered.

0b0001

Device.

0b0011

Normal Memory Non-Cacheable.

0b0110

Reserved.[a]

0b0111

Write Back no Write Allocate.

0b1111

Write Back Write Allocate.

[0]Shareable bit
0b0

Non-shareable.

0b1

Shareable.

[a] If Write Through is used in the MPU, it behaves as normal memory, non-cacheable, and its value is 0b0110.


Read address channel of AXI master 1, ARUSERM1[8:0]

Table 11.3 shows the bit encodings for ARUSERM1[8:0].

Table 11.3. ARUSERM1[8:0] encodings

BitsNameDescription
[8:7]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.

[6]Speculative linefill hintSpeculative linefill, used with L2C-310 Cache Controller.
[5]Reserved0b0
[4:1]Inner attributes
0b0000

Strongly Ordered.

0b0001

Device.

0b0011

Normal Memory Non-Cacheable.

0b0110

Reserved.[a]

0b0111

Write Back no Write Allocate.

0b1111

Write Back Write Allocate.

[0]Shareable bit
0b0

Non-shareable.

0b1

Shareable.

[a] If Write Through is used in the MPU, it behaves as normal memory, non-cacheable, and its value is 0b0110.


Peripheral read bus, ARUSERMP[8:0]

Table 11.4 shows the bit encodings for ARUSERMP[8:0].

Table 11.4. ARUSERMP[8:0] encodings

BitsNameDescription
[8:7]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.

[6:5]Reserved0b0
[4:1]Inner attributes
0b0000

Strongly Ordered.

0b0001

Device.

0b0011

Normal Memory Non-Cacheable.

0b0110

Write Through.

0b0111

Write Back no Write Allocate.

0b1111

Write Back Write Allocate.

[0]Shareable bit
0b0

Non-shareable.

0b1

Shareable.


Write address channel of AXI master 0, AWUSERM0[10:0]

Table 11.5 shows the bit encodings for AWUSERM0[10:0].

Table 11.5. AWUSERM0[10:0] encodings

BitsNameDescription
[10:9]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.

[8]Early BRESP Enable bitIndicates that the L2 slave can send an early BRESP answer to the write request. See Early BRESP.
[7:5]ReservedRAZ
[4:1]Inner attributes
0b0000

Strongly Ordered.

0b0001

Device.

0b0011

Normal Memory Non-Cacheable.

0b0110

Reserved.[a]

0b0111

Write Back no Write Allocate.

0b1111

Write Back Write Allocate.

[0]Shareable bit
0b0

Non-shareable.

0b1

Shareable.

[a] If Write Through is used in the MPU, it behaves as normal memory, non-cacheable, and its value is 0b0110.


Write address channel of AXI master 1, AWUSERM1[10:0]

Table 11.6 shows the bit encodings for AWUSERM1[10:0].

Table 11.6. AWUSERM1[10:0] encodings

BitsNameDescription
[10:9]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.

[8]Early BRESP Enable bitIndicates that the L2 slave can send an early BRESP answer to the write request. See Early BRESP.
[7:5]ReservedRAZ
[4:1]Inner attributes
0b0000

Strongly Ordered.

0b0001

Device.

0b0011

Normal Memory Non-Cacheable.

0b0110

Reserved.[a]

0b0111

Write Back no Write Allocate.

0b1111

Write Back Write Allocate.

[0]Shareable bit
0b0

Non-shareable.

0b1

Shareable.

[a] If Write Through is used in the MPU, it behaves as normal memory, non-cacheable, and its value is 0b0110.


Peripheral write bus, AWUSERMP[10:0]

Table 11.7 shows the bit encodings for AWUSERMP[10:0].

Table 11.7. AWUSERMP[10:0] encodings

BitsNameDescription
[10:9]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.

[8:5]ReservedRAZ
[4:1]Inner attributes
0b0000

Strongly Ordered.

0b0001

Device.

0b0011

Normal Memory Non-Cacheable.

0b0110

Reserved.[a]

0b0111

Write Back no Write Allocate.

0b1111

Write Back Write Allocate.

[0]Shareable bit
0b0

Non-shareable.

0b1

Shareable.

[a] If Write Through is used in the MPU, it behaves as normal memory, non-cacheable, and its value is 0b0110.


Write data channel of AXI master 0, WUSERM0[1:0]

Table 11.8 shows the bit encodings for WUSERM0[1:0].

Table 11.8. WUSERM0[1:0] encodings

BitsNameDescription
[1:0]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.


Write data channel of AXI master 1, WUSERM1[1:0]

Table 11.9 shows the bit encodings for WUSERM1[1:0].

Table 11.9. WUSERM1[1:0] encodings

BitsNameDescription
[1:0]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.


Peripheral write data bus, WUSERMP[1:0]

Table 11.10 shows the bit encodings for WUSERMP[1:0].

Table 11.10. WUSERMP[1:0] encodings

BitsNameDescription
[1:0]Transaction type
0b00

Processor 0 transaction.

0b10

Processor 1 transaction.

0b01

ACP transaction.

0b11

Reserved.


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