1.6. Redundant processor comparison

You can implement the Cortex-R7 MPCore processor with a second, redundant copy of most of the logic. The redundant logic includes a second processor that shares the input pins and the cache and TCM of the master processor, so only one set of cache and TCM is required. The redundant logic includes the individual processor logic, but not the ETM logic if the ETM is present. The redundant logic operates in lock-step with the processor, but does not directly affect the processor behavior in any way. The master processor drives the output pins and the RAMs. The redundant logic also includes a copy of

Comparison logic can be included at build time. This logic compares the outputs of the processor, SCU, and AXI TCM slave with those of their redundant copy. These comparators are enabled through the COMPENABLE input signal. If a fault occurs in either the main or redundant logic because of radiation or circuit failure, the comparison logic detects it and the output signal COMPFAULT is asserted. Used in conjunction with the RAM error detection schemes, this can help protect the system from faults. COMPENABLE can be asserted only after a initialization phase, see the ARM® Cortex®-R7 MPCore Configuration and Sign-Off Guide. See the ARM® Cortex®-R7 MPCore Integration Manual for more information about COMPENABLE and COMPFAULT or contact your system integrator.

ARM provides example comparison logic, but you can change this during implementation. If you are implementing a dual-redundant configuration, contact ARM for more information.

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